Digital Gaussian noise simulator
View Patent ↗A Gaussian noise is simulated by discrete analogue r i,j . A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude s i,j is calculated for each point based on α, i and j. The discrete analogue r i,j is based on a respective s i,j . Examples are given of α = 2 B - A 2 B and D>i≧0 and 2 C >j≧0, where B≧0, 2 B >A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j or s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
1. An integrated circuit for simulating a noise based on a random variable comprising:
a plurality of first generators each capable of generating a first plurality of discrete values;
a plurality of comparators, each comparator coupled to a respective one of the first generators to compare a discrete value generated by the respective first generator to a predetermined value, each comparator providing an output representative of whether the discrete value generated by the respective first generator is smaller than the predetermined value;
a selector responsive to a selected output of at least one of the comparators to supply a first integer value;
a second generator capable of generating a second plurality of discrete values; and
a memory responsive to the first integer value and respective ones of the second plurality of discrete values to provide a discrete analogue of the random variable.
2. The integrated circuit of claim 1 , further including
a third generator for generating a bit representative of a sign, and
a sign indicator for applying the sign representation to the discrete analogue.
3. The integrated circuit of claim 2 , wherein the bit representative of the sign is evaluated as (−1) u 1 , where u 1 is a pseudo-random variable generated by the third generator that provides values 0 and 1 with a probability of 0.5.
4. The integrated circuit of claim 1 , wherein the selector has D inputs and supplies the first integer value i, at least D−1 of which are from respective comparators, and the second generator generates 2 C −1 discrete values j, and wherein the memory is constructed to identify a magnitude for each of a plurality of points
s
i
,
j
=
1
-
α
i
+
α
i
·
1
-
α
2
C
·
j
,
where
α
=
2
B
-
A
2
B
and A, B, C and D are integers.
5. The integrated circuit of claim 4 , wherein each first generator generates 2 B discrete values, and each comparator compares the discrete value to A.
6. The integrated circuit of claim 1 , wherein the plurality of first generators comprises D−1 first generators, where D is an integer and each of the D−1 first generators generates respective discrete values x i representing one of x 0 , x 1 , . . . , x D−2 and having a uniformly-distributed pseudo-random value.
7. The integrated circuit of claim 1 wherein the first and second generators comprise pseudo-random generators.
8. An integrated circuit for simulating a noise based on a random variable comprising:
a plurality of first pseudo-random generators, each generating a pseudo-random discrete value;
a plurality of comparators, each comparator coupled to a respective one of the first generators to compare the discrete value generated by the respective first generator to a predetermined value, each comparator providing an output representative of a comparison between a magnitude of the discrete value generated by the respective first generator and the predetermined value;
a selector responsive to the output of at least one of the comparators to supply a first integer value;
a second pseudo-random generator capable of generating a further pseudo-random discrete value; and
a memory responsive to the first integer value and the further pseudo-random value to provide a discrete analogue of the random variable.
9. The integrated circuit of claim 8 , further including
a third generator for generating a bit representative of a sign, and
a sign indicator for applying the sign representation to the discrete analogue.
10. The integrated circuit of claim 9 , wherein the bit representative of the sign is evaluated as (−1) u 1 , where u 1 is a pseudo-random variable generated by the third generator that provides values 0 and 1 with a probability of 0.5.
11. The integrated circuit of claim 8 , wherein the selector has D inputs and supplies the first integer value i, at least D−1 of which are from respective comparators, and the second generator generates 2 C −1 discrete values j, and wherein the memory is constructed to identify a magnitude for each of a plurality of points
s
i
,
j
=
1
-
α
i
+
α
i
·
1
-
α
2
C
·
j
,
where
α
=
2
B
-
A
2
B
and A, B, C and D are integers.
12. The integrated circuit of claim 11 , wherein each first generator generates 2 B discrete values, and each comparator compares the pseudo-random discrete value to A.
13. The integrated circuit of claim 8 , wherein the plurality of first generators comprises D−1 first generators, where D is an integer and each of the D−1 first generators generates respective pseudo-random discrete values x i representing one of x 0 , x 1 , . . . , x D−2 and having a uniformly-distributed pseudo-random value.