Base platforms with combined ASIC and FPGA features and process of using the same
View Patent ↗A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
1. A process comprising steps of:
a) preparing a verified hardware description of a circuit to be embodied in a base integrated circuit platform and a separate die, wherein the base integrated circuit platform includes a single die that has both ASIC and FPGA modules, wherein the verified hardware description of the circuit comprises a plurality of functions, wherein the separate die is outside of the base integrated circuit platform;
b) separating the plurality of functions into standard functions and user-defined functions, wherein the user-defined functions comprise memory programmable functions and non-memory programmable functions;
c) assigning the standard functions to the separate die and the user-defined functions to the single die of the base integrated circuit platform;
d) for the user-defined functions, grouping the memory programmable functions for assignment to FPGA modules on the single die of the base integrated circuit platform;
e) for the user-defined functions, synthesizing the non-memory programmable functions to the ASIC modules and the grouped memory programmable functions to the FPGA modules on the single die of the base integrated circuit platform;
f) configuring the single die of the base integrated circuit platform by adding at least one metallization layer to configure the ASIC modules, and creating a configuration memory image to configure the FPGA modules; and
g) packaging the separate die with the single die of the configured base integrated circuit platform to form a system-in-package.
2. The process of claim 1 , further including, before step d), a step of: identifying the memory programmable functions.
3. The process of claim 2 , wherein step d) comprises steps of
annotating a module map of the hardware description to identify the memory programmable functions, and
grouping the memory programmable functions for assignment to FPGA modules based on the annotated module map.
4. The process of claim 1 , wherein step d) comprises steps of:
annotating a module map of the hardware description to identify the memory programmable functions, and
grouping the memory programmable functions for assignment to FPGA modules based on the annotated module map.
5. The process of claim 1 , further comprising:
programming at least one FPGA module of the FPGA modules with a memory programmable function to replace a non-memory programmable function assigned to at least one ASIC module of the ASIC modules, and
controlling outputs from the at least one FPGA module and the at least one ASIC module to output results from the at least one FPGA module in place of results from the at least one ASIC module.
6. The process of claim 5 , wherein controlling comprises:
applying input signals to the at least one FPGA module, which are connected to the at least one ASIC module for which the non-memory programmable function is being replaced by the memory-programmable function of the at least one FPGA module; and
controlling a multiplexer, which is connected to outputs from the at least one FPGA module and the at least one ASIC module to output results from the at least one FPGA module in place of results from the at least one ASIC module.
7. The process of claim 1 , further including steps of:
testing the synthesized FPGA modules to identify conformance to a specification for which the hardware description was prepared,
modifying the memory programmable functions for FPGA modules that are not in conformance to the specification, and
re-synthesizing the modified memory programmable functions to FPGA modules.
8. A process comprising:
a) preparing a hardware description of a circuit to perform a plurality of functions;
b) separating the plurality of functions into standard functions and user-defined functions, wherein the user-defined functions comprise memory programmable functions and non-memory programmable functions;
c) selecting a base integrated circuit platform comprising a single die having pre-diffused metal-programmable transistor fabric and firmware-configurable logic blocks, which are suitable for embodying the user-defined functions of the hardware description;
d) assigning the standard functions to a separate die outside of the base integrated circuit platform and the user-defined functions to the single die of the base integrated circuit platform;
e) for the user-defined functions, grouping memory programmable functions for assignment to the firmware-configurable logic blocks on the single die of the base integrated circuit platform;
f) for the user-defined functions, synthesizing the non-memory programmable functions to the pre-diffused metal-programmable transistor fabric and the grouped memory programmable functions to the firmware-configurable logic blocks on the single die of the base integrated circuit platform;
g) configuring the single die of the base integrated circuit platform by adding at least one metallization layer to configure the pre-diffused metal-programmable transistor fabric, and creating a configuration memory image to configure the firmware-configurable logic blocks; and
h) packaging the separate die with the single die of the configured base integrated circuit platform to form a system-in-package.
9. The process of claim 8 , wherein synthesizing comprises:
selectively connecting at least one of the firmware-configurable logic blocks to the metal-programmable transistor fabric to receive input signals that are connected to logic configured in the metal-programmable transistor fabric; and
coupling a multiplexer to the logic configured in the metal-programmable transistor fabric and the at least one firmware-configurable logic block such that the multiplexer is configured to selectively output results from either the logic configured in the metal-programmable transistor fabric or the at least one firmware-configurable logic block.