IP Library Granted Patent US 8,397,184
Granted Patent B2
US 8,397,184 · App. 12/248,677 · Granted Mar 12, 2013

Channel length scaling for footprint compatible digital library cell design

Inventor: Richard Schultz (Fort Collins, CO)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,397,184
App. No.
12/248,677
Granted
Mar 12, 2013
Kind
B2
Abstract

A library cell is designed, and then the width of the polys is increased, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The method can be used in association with a 45 nm digital library cell. Specifically, a library cell having 40 nm polys is designed, and then the width of each of the polys is increased by 5 nm to 45 nm, and the polys and contacts are shifted in order to maintain poly-to-poly and contact-to-poly spacing. The poly lines and contacts can be shifted by starting at the center and going out radially, or by beginning at the perimeter and moving radially inward. The method can be used with any library cell design which is entirely GDS based, including, for example, 32 nm library cell design.

Claims (9)

1. A GDS-based method of channel length scaling in library cell design, said GDS-based method comprising: using a GDS-based tool to design a library cell having a plurality of polys (polysilicon) and a plurality of contacts, wherein each of the polys are spaced away from each other, and wherein each of the contacts and polys are spaced away from each other; using the GDS-based tool to modify the library cell by increasing the width of the polys and using the GDS-based tool to shift the polys and the contacts such that poly-to-poly spacing is maintained and contact-to-poly spacing is maintained, wherein the step of shifting the polys and the contacts comprises at least one of; starting at a center of the polys and going out radially; and starting at a perimeter of the polys and moving radially inward.

2. The method as recited in claim 1 , wherein the step of increasing the width of the polys comprises increasing the width by 5 nm.

3. The method as recited in claim 1 , wherein the step of increasing the width of the polys comprises increasing the width from 40 nm to 45 nm.

4. The method as recited in claim 1 , wherein the step of shifting the polys and the contacts such that poly-to-poly spacing is maintained comprises maintaining the spacing between the polys at minimum allowed space.

5. The method as recited in claim 1 , wherein the step of shifting the polys and the contacts such that contact-to-poly spacing is maintained comprises maintaining the spacing between the contacts and polys at minimum allowed space.

6. The method as recited in claim 1 , wherein the step of shifting the polys and the contacts such that poly-to-poly spacing is maintained comprises maintaining the spacing between the polys at minimum and maintaining the spacing between the contacts and polys at minimum.

7. The method as recited in claim 1 , wherein the step of designing a library cell comprises designing a library cell which comprises metal-1 patterns, and the method comprises maintaining, and not changing, the metal-1 patterns.

8. The method as recited in claim 1 , wherein the step of designing a library cell comprises designing a library cell which comprises an N-active and Proactive sources and drains, and the method further comprises changing areas of the N-active and the P-active sources and drains.

9. The method as recited in claim 1 , wherein the step of designing a library cell comprises designing a library cell which comprises metal-1 patterns, an N-active and P-active, and the method comprises maintaining, and not changing, the metal-1 patterns, and the method comprises changing the areas of the N-active and the P-active sources and drains.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2013
From: SCHULTZ, RICHARD
To: LSI CORPORATION
Reel/Frame 029770/0064 →
Continuity (1)
Related Publication 20100095252A1 · Apr 15, 2010