IP Library Granted Patent US 8,196,086
Granted Patent B2
US 8,196,086 · App. 12/840,535 · Granted Jun 5, 2012

Granular channel width for power optimization

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Quick Facts
Patent No.
US 8,196,086
App. No.
12/840,535
Granted
Jun 5, 2012
Kind
B2
Abstract

A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Claims (32)

1. A storage medium recording a cell library comprising one or more cells that are readable by a computer and used by said computer to design an integrated circuit, a given one of said cells comprising:

a footprint; and

a channel width parameter of a channel width, wherein (i) said channel width parameter defines a range within which a tool varies said channel width in said given cell during a design flow of said integrated circuit based upon one or more power criteria without changing said footprint of said given cell and (ii) said cell library further comprises a lookup table comprising (a) said power criteria, (b) one or more performance criteria or (c) a combination of both said power criteria and said performance criteria.

2. The storage medium according to claim 1 , wherein said lookup table bounds said tool in adjusting (i) a power usage of said given cell, (ii) a performance of said given cell, or (iii) a combination of both said power usage and said performance of said given cell.

3. The storage medium according to claim 1 , wherein said lookup table bounds said tool in adjusting (i) a static power usage of said given cell, (ii) a dynamic power usage of said given cell, or (iii) a combination of both said static power usage and said dynamic power usage of said given cell.

4. The storage medium according to claim 1 , wherein said cell library comprises a plurality of said given cells.

5. The storage medium according to claim 1 , wherein said channel width parameter comprises a width of a diffusion area in said given cell.

6. The storage medium according to claim 1 , wherein a particular channel width of said given cell is adjusted to a different channel width after said given cell has been placed and routed.

7. A method of creating a cell library comprising one or more cells used to design an integrated circuit, said method comprising the steps of:

(A) storing a footprint of a given one of said cells in a storage medium using a computer; and

(B) storing a channel width parameter of a channel width in said given cell in said storage medium, wherein (i) said channel width parameter defines a range within which a tool varies said channel width in said given cell during a design flow of said integrated circuit based upon one or more power criteria without changing said footprint of said given cell and (ii) said cell library further comprises a lookup table comprising (a) said power criteria, (b) one or more performance criteria or (c) a combination of both said power criteria and said performance criteria.

8. The method according to claim 7 , wherein said lookup table bounds said tool in adjusting (i) a power usage of said given cell, (ii) a performance of said given cell, or (iii) a combination of both said power usage and said performance of said given cell.

9. The method according to claim 7 , wherein said lookup table bounds said tool in adjusting (i) a static power usage of said given cell, (ii) a dynamic power usage of said given cell, or (iii) a combination of both said static power usage and said dynamic power usage of said given cell.

10. The method according to claim 7 , wherein a dynamic power usage of said given cell is varied by said tool per a positive slack recovery.

11. The method according to claim 7 , wherein said channel width parameter comprises a width of a diffusion area in said given cell.

12. The method according to claim 7 , wherein a particular channel width of said given cell is adjusted to a different channel width after said given cell has been placed and routed.

13. A method of adjusting power in a design of an integrated circuit, said method comprising the steps of:

(A) performing a place and route of a plurality of cells in said design using a computer, wherein (i) a given one of said cells comprises (a) a footprint and (b) a channel width parameter of a channel width and (ii) said channel width parameter defines a range within which a tool varies said channel width in said given cell based on one or more power criteria without changing said footprint of said given cell;

(B) adjusting said channel width in said given cell with said tool; and

(C) finalizing said channel width in said given cell to create a final design of said integrated circuit, wherein a cell library of said cells comprises a lookup table comprising (i) said power criteria, (ii) one or more performance criteria or (iii) a combination of both said power criteria and said performance criteria.

14. The method according to claim 13 , wherein said tool adjusts said performance criteria of said given cell.

15. The method according to claim 13 , wherein said lookup table bounds said tool in adjusting (a) a power usage of said given cell, (b) a performance of said given cell, or (c) a combination of both said power usage and said performance of said given cell.

16. The method according to claim 13 , wherein said lookup table further comprise a plurality of power usages of said given cell and a plurality of performances of said given cell.

17. A storage medium recording a cell library comprising one or more cells that are readable by a computer and used by said computer to design an integrated circuit, a given one of said cells comprising:

a footprint; and

a channel width parameter of a channel width, wherein (i) said channel width parameter defines a range within which a tool varies said channel width in said given cell during a design flow of said integrated circuit based upon one or more power criteria without changing said footprint of said given cell and (ii) said cell library further comprises a lookup table that bounds said tool in adjusting (a) a static power usage of said given cell, (b) a dynamic power usage of said given cell, or (c) a combination of both said static power usage and said dynamic power usage of said given cell.

18. The storage medium according to claim 17 , wherein said given cell further comprises one or more performance criteria.

19. A method of adjusting power in a design of an integrated circuit, said method comprising the steps of:

(A) performing a place and route of a plurality of cells of a cell library in said design using a computer, wherein (i) a given one of said cells comprises (a) a footprint and (b) a channel width parameter of a channel width and (ii) said channel width parameter defines a range within which a tool varies said channel width in said given cell based on one or more power criteria without changing said footprint of said given cell;

(B) adjusting said channel width in said given cell with said tool; and

(C) finalizing said channel width in said given cell to create a final design of said integrated circuit, wherein said cell library comprises one or more lookup tables comprising (i) a plurality of power usages of said given cell and (ii) a plurality of performances of said given cell.

20. The method according to claim 19 , wherein said given cell further comprise one or more performance criteria.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2010
From: BROWN, JEFFREY S.; BYRN, JONATHAN W.; TURNER, MARK F.
To: LSI CORPORATION
Reel/Frame 024719/0359 →