IP Library Granted Patent US 8,239,813
Granted Patent B2
US 8,239,813 · App. 13/173,855 · Granted Aug 7, 2012

Method and apparatus for balancing signal delay skew

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,239,813
App. No.
13/173,855
Granted
Aug 7, 2012
Kind
B2
Abstract

A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

Claims (33)

1. A method comprising performing the following steps with a computing device:

receiving a netlist comprising components and connections among the components;

identifying a plurality of net groups, each comprising at least some of the connections for which equivalent routing is desired; and

for each net group, systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and comprising path fragments,

wherein routing comprises, for the connections of the net group, providing the same number of corresponding path fragments in a first of the connection paths in the net group as in a second of the connection paths in the net group, and routing the path fragments such that a plurality of the path fragments in the first connection path have equal lengths and equal orientations as corresponding path fragments in the second connection path.

2. The method of claim 1 , wherein some of the plurality of path fragments in each of the first and second connection paths are routed on different layers of a substrate and wherein routing comprises, for each of the plurality of path fragments of the first connection path, routing that path fragment in the same layer of the substrate as the corresponding path fragment of the second connection path.

3. The method of claim 1 , wherein

routing comprises routing all of the connection paths in all of the net groups simultaneously.

4. The method of claim 1 , wherein identifying a plurality of net groups comprises identifying a group of the connections having a common signal origin.

5. The method of claim 1 , wherein identifying a plurality of net groups comprises identifying a group of the connections having a parallel signal origin within the netlist.

6. The method of claim 1 , wherein each of the net groups corresponds to the connections between the components of a respective heterogeneous logic block within the netlist.

7. The method of claim 1 , wherein the steps of identifying a plurality of net groups and routing comprises a systematic, single-iteration process for reducing skew timing differences along the connection paths between the components of each of the net groups.

8. The method of claim 1 , wherein the step of routing the path fragments such that the plurality of the path fragments in the first connection path have equal lengths and equal orientations as corresponding path fragments in the second connection path is performed by adding a wire extension to at least one of the plurality of the path fragments in at least one of the first and second connection paths without changing placement of any of the components in the netlist.

9. The method of claim 1 , wherein:

the first connection path comprises a signal net extending from an output of a first component in the netlist and an input of a second component in the netlist;

the second connection path comprises a signal net extending from the output of the first component in the netlist and an input of a third component in the netlist; and

the first and second signal nets have the same number of path fragments, and corresponding path fragments in the first and second signal wires have equal lengths and equal orientations.

10. A non-transitory medium comprising executable instructions capable of being read and executed by a computing system and thereby configuring the computing system to receive a logic design and to provide a corresponding physical design embodying the logic design, wherein the computing system executing the instructions performs a method comprising:

receiving a netlist comprising components and connections among the components;

identifying a plurality of net groups, each comprising at least some of the connections for which equivalent routing is desired; and

for each net group, systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and comprising path fragments,

wherein routing comprises, for the connections of the net group, providing the same number of corresponding path fragments in a first of the connection paths in the net group as in a second of the connection paths in the net group, and routing the path fragments such that a plurality of the path fragments in the first connection path have equal lengths and equal orientations as corresponding path fragments in the second connection path.

11. The non-transitory medium of claim 10 , wherein:

routing comprises routing all of the connection paths in all of the net groups simultaneously.

12. The non-transitory medium of claim 10 , wherein identifying a plurality of net groups comprises identifying a group of the connections having a common signal origin.

13. The non-transitory medium of claim 10 , wherein identifying a plurality of net groups comprises identifying a group of the connections having a parallel signal origin within the netlist.

14. The non-transitory medium of claim 10 , wherein each of the net groups corresponds to the connections between the components of a respective heterogeneous logic block within the netlist.

15. The non-transitory medium of claim 10 , wherein the steps of identifying a plurality of net groups and routing comprises a systematic, single-iteration process for reducing skew timing differences along the connection paths between the components of each of the net groups.

16. The non-transitory medium of claim 10 , wherein the step of routing the path fragments such that the plurality of the path fragments in the first connection path have equal lengths and equal orientations as corresponding path fragments in the second connection path is performed by adding a wire extension to at least one of the plurality of the path fragments in at least one of the first and second connection paths without changing placement of any of the components in the netlist.

17. The non-transitory medium of claim 10 , wherein:

the first connection path comprises a signal net extending from an output of a first component in the netlist and an input of a second component in the netlist;

the second connection path comprises a signal net extending from the output of the first component in the netlist and an input of a third component in the netlist; and

the first and second signal nets have the same number of path fragments, and corresponding path fragments in the first and second signal wires have equal lengths and equal orientations.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (2)
Division 12015925 · Jan 17, 2008
Related Publication 20110258587A1 · Oct 20, 2011