Circuit timing analysis incorporating the effects of temperature inversion
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner.
1. A computer-implemented method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
for each cell in the circuit, performing, by a processor, cell library timing characterization for at least prescribed first and second temperatures, the first and second temperatures corresponding to at least first and second process, voltage and temperature (PVT) corners in the cell library;
calculating, by a processor, a cell delay for each cell in the circuit, the cell delay calculation being a function of temperature for each instance of the at least one cell; and
adding a margin to the cell delay for each cell in the circuit when the temperature is a temperature other than the at least one of the first and second temperatures, the cell library timing characterization being modified as a function of the margin corresponding to each cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of timing characterization of the circuit.
2. The method of claim 1 , wherein the step of adding a margin to the cell delay for each cell in the circuit is performed during run-time of the cell library timing characterization.
3. The method of claim 1 , wherein the margin added to the cell delay for each cell in the circuit comprises a de-rating factor which incorporates effects of temperature on cell timing of the cell.
4. The method of claim 1 , wherein the step of calculating the cell delay comprises:
determining a temperature map corresponding to a physical layout of the at least one cell in the circuit; and
determining the cell delay of the at least one cell as a function of a temperature at a physical location of the at least one cell.
5. The method of claim 1 , further comprising incorporating the cell delay calculation into the timing characterization for the at least one cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of the timing characterization.
6. A computer-implemented method for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the method comprising the steps of:
for each cell in the circuit, performing, by a processor, cell library timing characterization for at least prescribed first and second temperatures, the first and second temperatures corresponding to at least first and second process, voltage and temperature (PVT) corners in the cell library;
calculating, by a processor, a cell delay for each cell in the circuit, the cell delay calculation being a function of temperature for each instance of the at least one cell; and
adding a margin to the cell delay for each cell in the circuit, the cell library timing characterization being modified as a function of the margin corresponding to each cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of timing characterization of the circuit;
wherein the step of calculating the cell delay comprises:
determining a temperature map corresponding to a physical layout of the at least one cell in the circuit;
determining the cell delay of the at least one cell as a function of a temperature at a physical location of the at least one cell;
determining a first delay of the at least one cell at the first prescribed temperature;
determining a second delay of the at least one cell at the second prescribed temperature; and
interpolating between the first and second delays to determine the cell delay of the at least one cell at the temperature at the physical location of the cell.
7. The method of claim 6 , wherein the step of interpolating comprises scaling the first and second delays corresponding to the first and second PVT corners, respectively, in the cell library.
8. A timing characterization system for increasing an accuracy of timing characterization of a circuit including at least one cell in a cell library, the system comprising:
a memory device storing a plurality of instructions embodying the system and an application; and
a processor configured to receive the application and execute the plurality of instructions to perform a method comprising:
for each cell in the circuit, performing cell library timing characterization for at least prescribed first and second temperatures, the first and second temperatures corresponding to at least first and second process, voltage and temperature (PVT) corners in the cell library;
calculating a cell delay for each cell in the circuit, the cell delay calculation being a function of temperature for each instance of the at least one cell; and
adding a margin to the cell delay for each cell in the circuit, the cell library timing characterization being modified as a function of the margin corresponding to each cell in the circuit to take into account effects of temperature inversion and thereby increase the accuracy of timing characterization of the circuit;
wherein the step of calculating the cell delay comprises:
determining a temperature map corresponding to a physical layout of the at least one cell in the circuit;
determining the cell delay of the at least one cell as a function of a temperature at a physical location of the at least one cell;
determining a first delay of the at least one cell at the first prescribed temperature;
determining a second delay of the at least one cell at the second prescribed temperature; and
interpolating between the first and second delays to determine the cell delay of the at least one cell at the temperature at the physical location of the cell.