IP Library Granted Patent US 8,372,723
Granted Patent B2
US 8,372,723 · App. 13/222,877 · Granted Feb 12, 2013

Bipolar device having buried contacts

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Quick Facts
Patent No.
US 8,372,723
App. No.
13/222,877
Granted
Feb 12, 2013
Kind
B2
Abstract

This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.

Claims (21)

1. A method of manufacturing a semiconductor device, comprising:

forming a collector for a bipolar transistor within a semiconductor substrate, wherein the collector excludes a collector tub;

forming an isolation region under the collector;

forming a contact trench within the collector;

forming a diffusion buried contact region within the trench, at least a portion of the diffusion buried contact region located within the trench and extending along sidewalls of the trench, the diffusion buried contact region extending into the collector to a depth sufficient to contact and make electrical connection with the collector

forming a base within the collector;

forming at least first and second bipolar transistor emitter structures on a surface of the semiconductor substrate and over the base and the collector and having a common base contact region located in the base and between the at least first and second bipolar transistors;

and

forming a contact plug that extends into the collector to the depth to contact the diffusion buried contact region within the trench.

2. The method recited in claim 1 , wherein the diffusion buried contact region is formed subsequent to forming the at least first and second bipolar transistor emitter structures.

3. The method recited in claim 1 , wherein forming the diffusion buried contact region includes forming the trench within the collector to a depth of at least about 0.050 microns.

4. The method recited in claim 3 , wherein the trench is formed using an etch process that patterns the at least first and second bipolar transistor emitter structures over the collector.

5. The method recited in claim 1 , wherein the depth extends to a peak concentration region of the collector.

6. The method recited in claim 5 , wherein a depth of the peak concentration ranges from about 4 microns to about 9 microns from an upper surface of the semiconductor substrate.

7. The method recited in claim 1 , wherein the at least first and second bipolar transistor emitter structures form a portion of vertical bipolar transistors.

8. The method recited in claim 1 , wherein forming the buried contact includes forming an opening in an oxide layer located over the collector, the opening exposing a surface of the semiconductor substrate.

9. The method recited in claim 8 , wherein the buried contact is formed through an oxide isolation region located over the collector.

10. The method recited in claim 1 , further includes forming a plurality of bases and emitters for a plurality of bipolar transistors, wherein the bipolar transistors form a portion of an integrated circuit and the method further includes:

forming non-bipolar transistors over the semiconductor substrate;

forming dielectric layers over the non-bipolar transistors and bipolar transistors; and

forming interconnects in the dielectric layers that electrically connect the non-bipolar and bipolar transistors, wherein a portion of the interconnects forms a portion of each the buried contact associated with each of the plurality of bipolar transistors.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CERTIFICATE OF CONVERSION AND FORMATION Recorded Oct 16, 2012
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 029135/0123 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2011
From: BARTELS, JENNIFER
To: PENGUIN IP HOLDINGS INC.
Reel/Frame 026949/0827 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: DYSON, MARK; KERR, DANIEL C.; ROSSI, NACE M.
To: AGERE SYSTEMS INC.
Reel/Frame 026840/0164 →