Patent Assignment
Reel/Frame 044886/0608
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2017-12-17
Received: 2017-12-17
Pages: 104
Assignors
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Executed: 2017-12-08
BROADCOM CORPORATION
Executed: 2017-12-08
Assignee
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE., SUITE 1600, CHICAGO, IL, 60611, UNITED STATES
Covered Applications
(100)
METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
App. No. 13/775,922
→
Maskless Vortex Phase Shift Optical Direct Write Lithography
App. No. 13/722,648
→
SEMICONDUCTOR DEVICE AND PROCESS FOR REDUCING DAMAGING BREAKDOWN IN GATE DIELECTRICS
App. No. 13/311,299
→
MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
App. No. 13/253,554
→
BIPOLAR DEVICE HAVING BURIED CONTACTS
App. No. 13/222,877
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 13/110,581
→
LOGIC-BASED EDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS
App. No. 13/046,973
→
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 13/026,528
→
MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK
App. No. 12/953,624
→
HYBRID BUMP CAPACITOR
App. No. 12/885,722
→
CHIP IDENTIFICATION USING TOP METAL LAYER
App. No. 12/741,839
→
CUB eDRAM Cell With Local Interconnects To Reduce Stacked Contact Parasitics Impact
App. No. 61/350,494
→
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
App. No. 12/764,004
→
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 12/727,304
→
TRANSISTOR FABRICATION METHOD
App. No. 12/689,749
→
METHOD FOR SEPARATING A SEMICONDUCTOR WAFER INTO INDIVIDUAL SEMICONDUCTOR DIES USING AN IMPLANTED IMPURITY
App. No. 12/618,936
→
INTERDIGITATED CAPACITORS
App. No. 12/616,050
→
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
App. No. 12/610,733
→
METHOD CHARACTERIZING MATERIALS FOR A TRENCH ISOLATION STRUCTURE HAVING LOW TRENCH PARASITIC CAPACITANCE
App. No. 12/574,426
→
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
App. No. 12/574,479
→
METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
App. No. 12/555,082
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 12/506,746
→
METHOD TO REDUCE COLLECTOR RESISTANCE OF A BIPOLAR TRANSISTOR AND INTEGRATION INTO A STANDARD CMOS FLOW
App. No. 12/523,368
→
METHOD FOR ABATING EFFLUENT FROM AN ETCHING PROCESS
App. No. 12/502,057
→
METHOD TO IMPROVE WRITER LEAKAGE IN SIGE BIPOLAR DEVICE
App. No. 12/476,994
→
INTEGRATED CIRCUIT INDUCTORS WITH REDUCED MAGNETIC COUPLING
App. No. 12/516,301
→
METHOD OF FABRICATING A VERTICAL TRANSISTOR AND CAPACITOR
App. No. 12/319,603
→
FILL PATTERNING FOR SYMMETRICAL CIRCUITS
App. No. 12/339,407
→
ELECTRICAL DEVICES HAVING ADJUSTABLE CAPACITANCE
App. No. 12/253,403
→
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 12/243,137
→
METHODS AND STRUCTURE FOR FORMING COPPER BARRIER LAYERS INTEGRAL WITH SEMICONDUCTOR SUBSTRATES STRUCTURES
App. No. 12/191,171
→
YIELD PROFILE MANIPULATOR
App. No. 12/117,379
→
TRANSISTOR FABRICATION METHOD
App. No. 12/114,589
→
Substrate Laser Marking
App. No. 12/034,750
→
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL
App. No. 12/021,728
→
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
App. No. 11/964,920
→
METHOD OF TREATING METAL AND METAL SALTS TO ENABLE THIN LAYER DEPOSITION IN SEMICONDUCTOR PROCESSING
App. No. 11/939,482
→
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
App. No. 11/937,199
→
SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
App. No. 11/927,978
→
DUAL-GATE METAL-OXIDE-SEMICONDUCTOR DEVICE
App. No. 11/927,950
→
SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
App. No. 11/926,469
→
SEMICONDUCTOR DEVICE WITH CONSTRICTED CURRENT PASSAGE
App. No. 11/872,347
→
APPARATUS FOR CONFINING INDUCTIVELY COUPLED SURFACE CURRENTS
App. No. 11/856,196
→
CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE
App. No. 11/853,417
→
REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
App. No. 11/827,807
→
OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
App. No. 11/769,486
→
INTEGRATED CIRCUIT WITH METAL SILICIDE REGIONS
App. No. 11/821,396
→
FABRICATION METHOD
App. No. 11/809,873
→
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
App. No. 11/809,686
→
GUARD RING FOR IMPROVED MATCHING
App. No. 11/748,569
→
HYBRID BUMP CAPACITOR
App. No. 11/741,195
→
DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
App. No. 11/736,402
→
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
App. No. 11/733,673
→
Planarization with reduced dishing
App. No. 11/695,169
→
SEMICONDUCTOR TEST DEVICE WITH HEATING CIRCUIT
App. No. 11/673,714
→
METHOD TO IMPROVE WRITER LEAKAGE IN A SIGE BIPOLAR DEVICE
App. No. 11/673,645
→
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
App. No. 11/670,031
→
FORMATION OF AN INTEGRATED CIRCUIT STRUCTURE WITH REDUCED DISHING IN METALLIZATION LEVELS
App. No. 11/649,015
→
PROCESS FOR MAKING AN ON-CHIP VACUUM TUBE DEVICE
App. No. 11/649,197
→
III-V POWER FIELD EFFECT TRANSISTORS
App. No. 11/641,507
→
PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
App. No. 11/542,864
→
METHOD OF ELECTRICAL TESTING OF AN INTERGRATED CIRCUIT WITH AN ELECTRICAL PROBE
App. No. 11/540,056
→
DIFFERENTIAL INDUCTOR FOR USE IN INTEGRATED CIRCUITS
App. No. 11/535,501
→
FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
App. No. 11/527,108
→
BIPOLAR DEVICE HAVING BURIED CONTACTS
App. No. 11/533,785
→
DEFECT IDENTIFICATION SYSTEM AND METHOD FOR REPAIRING KILLER DEFECTS IN SEMICONDUCTOR DEVICES
App. No. 11/519,614
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TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING
App. No. 11/506,659
→
METHOD FOR FORMING MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS
App. No. 11/458,270
→
METHOD TO IMPROVE METAL DEFECTS IN SEMICONDUCTOR DEVICE FABRICATION
App. No. 11/427,494
→
OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
App. No. 11/473,627
→
SEMICONDUCTOR DEVICE AND PROCESS FOR REDUCING DAMAGING BREAKDOWN IN GATE DIELECTRICS
App. No. 11/425,295
→
SELECTIVE LASER ANNEALING OF SEMICONDUCTOR MATERIAL
App. No. 11/438,493
→
INTERCONNECT DIELECTRIC TUNING
App. No. 11/419,548
→
A METHOD OF FORMING A SPIRAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE
App. No. 11/419,252
→
A VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
App. No. 11/419,356
→
INTEGRATED CIRCUIT WITH A TRENCH CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE
App. No. 11/383,670
→
APPARATUS FOR WAFER PATTERNING TO REDUCE EDGE EXCLUSION ZONE
App. No. 11/383,171
→
DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
App. No. 11/418,873
→
Adjustable Transmission Phase Shift Mask
App. No. 11/381,409
→
TEST SEMICONDUCTOR DEVICE AND METHOD FOR DETERMINING JOULE HEATING EFFECTS IN SUCH A DEVICE
App. No. 11/403,750
→
WAFER CHUCKING APPARATUS FOR SPIN PROCESSOR
App. No. 11/403,137
→
Vertical replacement-gate junction field-effect transistor
App. No. 11/390,015
→
PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
App. No. 11/385,156
→
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING IMPROVED PERFORMANCE AND RELIABILITY
App. No. 11/348,597
→
CROSS-FILL PATTERN FOR METAL FILL LEVELS, POWER SUPPLY FILTERING, AND ANALOG CIRCUIT SHIELDING
App. No. 11/339,540
→
PLANARIZATION WITH REDUCED DISHING
App. No. 11/337,460
→
Formation of an integrated circuit structure with reduced dishing in metallization levels
App. No. 60/756,056
→
METHOD AND APPARATUS FOR DIVERTING VOID DIFFUSION IN INTEGRATED CIRCUIT CONDUCTORS
App. No. 11/323,398
→
EMBEDDED TEST CIRCUITRY AND A METHOD FOR TESTING A SEMICONDUCTOR DEVICE FOR BREAKDOWN, WEAROUT OR FAILURE
App. No. 11/273,857
→
METHOD OF DESIGN BASED PROCESS CONTROL OPTIMIZATION
App. No. 11/265,040
→
MULTI-SURFACED PLATE-TO-PLATE CAPACITOR AND METHOD OF FORMING SAME
App. No. 11/266,133
→
INTERDIGITADED CAPACITORS
App. No. 11/265,062
→
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
App. No. 11/262,173
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 11/258,253
→
APPARATUS TO PASSIVATE INDUCTIVELY OR CAPACITIVELY COUPLED SURFACE CURRENTS UNDER CAPACITOR STRUCTURES
App. No. 11/248,509
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INTEGRATED CIRCUIT WITH DEPLETION MODE JFET
App. No. 11/237,095
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CALIBRATION STANDARD FOR TRANSMISSION ELECTRON MICROSCOPY
App. No. 11/237,410
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Shallow trench isolation structures and a method for forming shallow trench isolation structures
App. No. 11/230,188
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METHOD OF FORMING A LOW K POLYMER E-BEAM PRINTABLE MECHANICAL SUPPORT
App. No. 11/225,310
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Temperature control system
App. No. 11/210,986
→