Interconnect dielectric tuning
An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
1. In an integrated circuit, the improvement comprising:
an etch stop layer overlying front end processing layers of the integrated circuit, support structures disposed so as to support electrically conductive interconnects on various levels of the integrated circuit,
substantially complete voids disposed between the interconnects, caused by removing substantially all non electrically conductive layers above the etch stop layer that were formed during fabrication of the interconnects, and
a passivation layer overlying the interconnects, the passivation layer forming a void, wherein the void is filled with one of an inert gas and a vacuum.
2. The integrated circuit of claim 1 , wherein the etch stop layer is formed of at least one of silicon nitride and silicon carbide.
3. The integrated circuit of claim 1 , wherein the support structures are formed at least in part of a material that is used to form the interconnects.
4. The integrated circuit of claim 1 , wherein at least one of the support structures and the interconnects are formed of metal.