IP Library Granted Patent US 8,049,282
Granted Patent B2
US 8,049,282 · App. 11/533,785 · Granted Nov 1, 2011

Bipolar device having buried contacts

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Quick Facts
Patent No.
US 8,049,282
App. No.
11/533,785
Granted
Nov 1, 2011
Kind
B2
Abstract

The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.

Claims (34)

1. A semiconductor device, comprising:

a collector for a bipolar transistor located within a semiconductor substrate, wherein a collector tub is not present in the collector;

a diffusion buried contact region, at least a portion of which is located in a trench that extends into the collector to a depth sufficient to adequately contact the collector and that makes electrical connection within the collector, wherein the diffusion buried contact region extends along sidewalls of the trench;

a base region located within the collector;

at least first and second bipolar transistor emitter structures located on a surface of the semiconductor substrate and over the base and the collector and having a common base contact region located in the base and between the at least first and second bipolar transistors; and

a contact plug that extends into the collector to the depth to contact the diffusion buried contact region within the trench.

2. The device recited in claim 1 , wherein the diffusion buried contact region extends to a depth of at least about 0.05 microns into the collector.

3. The device recited in claim 1 , wherein the diffusion buried contact region further includes a contact junction located within the collector at the depth and the device further includes a dielectric layer located over the at least first and second bipolar transistor emitter structures and wherein a portion of the dielectric layer is located in the trench.

4. The device recited in claim 3 , wherein the diffusion buried contact region extends to a peak concentration region of the collector.

5. The device recited in claim 1 , wherein the diffusion buried contact region extends through an oxide isolation region located over the collector.

6. The device recited in claim 1 , further including a plurality of the bases and the emitter structures that form a plurality of bipolar transistors wherein the plurality of bipolar transistors form a portion of an integrated circuit, and the device further comprising:

non-bipolar transistors located over the semiconductor substrate;

dielectric layers located over the non-bipolar transistors and bipolar transistors; and

interconnects located in the dielectric layers that electrically connect to the non-bipolar and bipolar transistors, wherein a portion of the interconnects forms a portion of each of the buried contacts associated with each of the plurality of bipolar transistors.

7. A semiconductor device, comprising:

a collector for a bipolar transistor located within a semiconductor substrate, wherein a collector tub is not present in the collector;

a diffusion buried contact region, at least a portion of which is located in a trench that extends into the collector to a depth sufficient to adequately contact the collector and that makes electrical connection within the collector, wherein the diffusion buried contact region extends along the bottom and sidewalls of the trench;

a base region located within the collector;

at least a first biploar transistor emitter structure located on a surface of the semiconductor substrate and over the base and the collector; and

a contact plug that extends into the collector to the depth to contact the diffusion buried contact region within the trench.

8. The device recited in claim 7 , wherein the diffusion buried contact region extends to a depth of at least about 0.05 microns into the collector.

9. The device recited in claim 7 , wherein the diffusion buried contact region further includes a contact junction located within the collector at the depth and the device further includes a dielectric layer located over the at least first emitter structure and wherein a portion of the dielectric layer is located in the trench.

10. The device recited in claim 9 , wherein the diffusion buried contact region extends to a peak concentration region of the collector.

11. A semiconductor device, comprising:

a collector for a bipolar transistor located within a semiconductor substrate, wherein a collector tub is not present in the collector;

a diffusion buried contact region having a width less than about 1.6 microns and at least a portion of which is located in a trench that extends into the collector to a depth sufficient to adequately contact the collector and that makes electrical connection within the collector, wherein the diffusion buried contact region extends along the bottom and sidewalls of the trench;

a base region located within the collector;

at least a first biploar transistor emitter structure located on a surface of the semiconductor substrate and over the base and the collector; and

a contact plug that extends into the collector to the depth to contact the diffusion buried contact region within the trench.

12. The device recited in claim 11 , wherein the diffusion buried contact region extends to a depth of at least about 0.05 microns into the collector.

13. The device recited in claim 12 , wherein the depth of the diffusion buried contact region is about 1 micron.

14. The device recited in claim 11 , wherein the diffusion buried contact region further includes a contact junction located within the collector at the depth and the device further includes a dielectric layer located over the at least first emitter structure and wherein a portion of the dielectric layer is located in the trench.

15. The device recited in claim 11 , wherein the diffusion buried contact region extends to a peak concentration region of the collector.

16. The device recited in claim 15 , wherein a depth of the peak concentration ranges from about 4 microns to about 9 microns.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2006
From: DYSON, MARK; KERR, DANIEL C; ROSSI, NACE M
To: AGERE SYSTEMS INC.
Reel/Frame 018399/0566 →