IP Library Granted Patent US 7,557,010
Granted Patent B2
US 7,557,010 · App. 11/673,645 · Granted Jul 7, 2009

Method to improve writer leakage in a SiGe bipolar device

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Quick Facts
Patent No.
US 7,557,010
App. No.
11/673,645
Granted
Jul 7, 2009
Kind
B2
Abstract

The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

Claims (50)

1. A method of manufacturing a semiconductor device, comprising:

conducting an etch through an opening in an emitter window in an emitter region to form a cavity from an underlying oxide layer, the etch exposing a doped tub;

forming a first silicon/germanium (SiGe) layer within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer, the first SiGe layer having a concentration of Ge therein;

forming a second graded SiGe layer over the first SiGe layer; and

forming a capping layer over the second SiGe layer.

2. The method recited in claim 1 , wherein adjusting the process parameter includes forming the first SiGe layer to a thickness that is less than 35 nm.

3. The method recited in claim 2 , wherein the thickness ranges from about 26 nm to about 34 nm.

4. The method recited in claim 3 , wherein a concentration of Ge in the first SiGe layer is about 12% by weight.

5. The method recited in claim 1 , wherein adjusting includes adjusting a flow rate of Ge such that a concentration of Ge in the first SiGe layer ranges from about 5% to about 10% by weight.

6. The method recited in claim 5 , wherein a thickness of the first SiGe layer ranges from about 26 nm to about 43 nm.

7. The method recited in claim 1 , wherein the second graded SiGe layer is located on the first SiGe layer and has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.

8. A semiconductor device, comprising:

a bipolar transistor region, including:

a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration and wherein a thickness of the first SiGe layer is less than 35 nm and has a strain associated therewith;

a second SiGe layer located over; and

a silicon capping layer over the second SiGe layer; and

an emitter layer located over the silicon capping layer; and

a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.

9. The device recited in claim 8 , wherein the Ge concentration of the first SiGe layer is about 12% by weight.

10. The device recited in claim 8 , wherein the thickness ranges from about 26 nm to about 34 nm.

11. The device recited in claim 8 , wherein the Ge concentration of the first SiGe ranges from about 5% to about 10% by weight.

12. The device recited in claim 8 , wherein, the second SiGe layer has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.

13. A semiconductor device, comprising:

a bipolar transistor region, including:

a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration that ranges from about 5% to about 10% by weight and has a strain associated therewith;

a second SiGe layer located over the first SiGe layer; and

a silicon capping layer over the second SiGe layer; and

an emitter layer located over the silicon capping layer; and

a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.

14. The device recited in claim 13 , wherein a thickness of the first SiGe layer ranges from about 35 nm to about 43 nm.

15. The device recited in claim 13 , wherein the Ge concentration of the first Si/Ge layer is about 7% by weight.

16. The device recited in claim 13 , wherein the thickness of the first Si/Ge layer ranges from about 26 nm to about 34 nm.

17. The device recited in claim 13 , wherein the second SiGe layer has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.

18. A method of manufacturing a semiconductor device, comprising:

forming an emitter for bipolar transistors in a bipolar transistor region, including:

conducting an etch through an opening in an emitter window located in an emitter region to form a cavity from an underlying oxide layer, the etch exposing a collector tub;

forming a first silicon/germanium (SiGe) layer within the cavity and over the collector tub by adjusting a process parameter to induce a strain in the first SiGe layer, the first SiGe layer having a concentration of Ge therein;

forming a graded second SiGe layer over the first SiGe layer;

forming a capping layer over the second SiGe layer;

forming an emitter layer over the capping layer; and

forming non-bipolar transistors in a non-bipolar region, including:

forming gate electrodes over non-bipolar transistor wells; and

forming source/drains in the wells,

conducting a second implant through the openings to place the dopant in the tubs of the vertical bipolar transistor region and form tubs in the second NMOS transistor region, such that the dopant concentration in the tubs of the vertical bipolar transistor region is greater than the dopant concentration in the tubs of the second NMOS transistor region.

19. The method recited in claim 18 , wherein adjusting the process parameter includes forming the first SiGe layer to a thickness that is less than 35 nm.

20. The method recited in claim 18 , wherein the thickness ranges from about 26 nm to about 34 nm.

21. The method recited in claim 20 , wherein a concentration of Ge in the first SiGe layer is about 12% by weight.

22. The method recited in claim 18 , wherein adjusting includes adjusting a flow rate of Ge such that a concentration of Ge in the first SiGe layer ranges from about 5% to about 10% weight.

23. The method recited in claim 22 , wherein a thickness of the first SiGe layer ranges from about 26 nm to about 43 nm.

24. The method recited in claim 18 , wherein the second graded SiGe layer is located on the first SiGe layer and has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.

Assignments (11)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2007
From: CHEN, ALAN S.; DYSON, MARK; ROSSI, NACE M.; SINGH, RANBIR
To: AGERE SYSTEMS INC.
Reel/Frame 018879/0436 →