IP Library › Assignment 060885/0001
Patent Assignment
Reel/Frame 060885/0001

SECURITY INTEREST

Recorded: 2022-04-15 Received: 2022-04-15 Pages: 253
Assignor
Assignees
HILCO PATENT ACQUISITION 56, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
BELL NORTHERN RESEARCH, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
Covered Applications (100)
SEALING STRUCTURES FOR LIGHT-EMITTING DIODE PACKAGES
App. No. 17/821,881
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PLUGGABLE MODULE HAVING EMI PREVENTION FINS IN AIRFLOW CHANNEL
App. No. 16/992,782
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RECEPTACLE ASSEMBLY AND THERMAL-TRANSFER ASSEMBLY
App. No. 16/581,796
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ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS
App. No. 14/073,526
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SENSE PIN FOR AN ELECTRICAL CONNECTOR
App. No. 13/784,136
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Maskless Vortex Phase Shift Optical Direct Write Lithography
App. No. 13/722,648
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INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
App. No. 13/443,691
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METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
App. No. 13/428,540
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CIRCUITS AND METHODS FOR IMPROVED FET MATCHING
App. No. 13/368,985
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BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
App. No. 13/348,415
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MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
App. No. 13/253,554
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HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
App. No. 13/149,122
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 13/110,581
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ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS
App. No. 13/119,005
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 13/026,528
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INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
App. No. 12/947,948
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EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE
App. No. 12/912,791
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Digitally Obtaining Contours of Fabricated Polygons
App. No. 12/890,336
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DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS
App. No. 12/839,148
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THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRNASISTORS FORMED ACCORDING TO THE METHOD
App. No. 12/832,110
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METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE
App. No. 12/680,017
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BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
App. No. 12/728,412
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 12/727,304
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TRANSISTOR FABRICATION METHOD
App. No. 12/689,749
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BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE
App. No. 12/652,560
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INTERDIGITATED CAPACITORS
App. No. 12/616,050
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STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
App. No. 12/610,733
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METHOD CHARACTERIZING MATERIALS FOR A TRENCH ISOLATION STRUCTURE HAVING LOW TRENCH PARASITIC CAPACITANCE
App. No. 12/574,426
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METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE
App. No. 12/555,082
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DIELECTRIC ETCHING
App. No. 12/546,855
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 12/506,746
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HIGH-DENSITY FIELD EMISSION ELEMENTS AND A METHOD FOR FORMING SAID EMISSION ELEMENTS
App. No. 12/506,090
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METHOD TO IMPROVE WRITER LEAKAGE IN SIGE BIPOLAR DEVICE
App. No. 12/476,994
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ELECTRONIC PRESSURE-SENSING DEVICE
App. No. 12/465,309
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ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
App. No. 12/356,600
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PROGRAMMABLE NANOTUBE INTERCONNECT
App. No. 12/354,768
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METHOD OF FABRICATING A VERTICAL TRANSISTOR AND CAPACITOR
App. No. 12/319,603
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HOT-ELECTRON INJECTION TESTING OF TRANSISTORS ON A WAFER
App. No. 12/344,016
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INDUCTOR FORMED IN AN INTEGRATED CIRCUIT
App. No. 12/340,813
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MATERIAL REMOVING PROCESSES IN DEVICE FORMATION AND THE DEVICES FORMED THEREBY
App. No. 12/290,054
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METHOD TO REDUCE BORON PENETRATION IN A SiGe BIPOLAR DEVICE
App. No. 12/256,677
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MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
App. No. 12/243,137
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THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTOR FORMED ACCORDING TO THE METHOD
App. No. 12/208,929
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PSEUDO LOW VOLUME RETICLE (PLVR) DESIGN FOR ASIC MANUFACTURING
App. No. 12/204,290
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METHODS AND STRUCTURE FOR FORMING COPPER BARRIER LAYERS INTEGRAL WITH SEMICONDUCTOR SUBSTRATES STRUCTURES
App. No. 12/191,171
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MASK SET FOR VARIABLE MASK FIELD EXPOSURE
App. No. 12/167,381
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APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
App. No. 12/140,773
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METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS
App. No. 12/156,281
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YIELD PROFILE MANIPULATOR
App. No. 12/117,379
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TRANSISTOR FABRICATION METHOD
App. No. 12/114,589
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HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
App. No. 12/112,076
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METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
App. No. 12/018,849
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STRUCTURE AND METHOD FOR IMPROVED HEAT CONDUCTION FOR SEMICONDUCTOR DEVICES
App. No. 11/968,693
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SYSTEM OF USING OFFSET GAGE FOR CMP POLISHING PAD ALIGNMENT AND ADJUSTMENT
App. No. 11/968,930
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SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES
App. No. 11/960,554
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METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
App. No. 11/999,168
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METHOD OF TREATING METAL AND METAL SALTS TO ENABLE THIN LAYER DEPOSITION IN SEMICONDUCTOR PROCESSING
App. No. 11/939,482
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VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
App. No. 11/937,199
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SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
App. No. 11/927,978
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DUAL-GATE METAL-OXIDE-SEMICONDUCTOR DEVICE
App. No. 11/927,950
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Method of isolation for acoustic resonator device
App. No. 11/906,196
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CIRCUITS AND METHODS FOR IMPROVED FET MATCHING
App. No. 11/838,546
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CONTROLLING OVERSPRAY COATING IN SEMICONDUCTOR DEVICES
App. No. 11/832,711
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REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
App. No. 11/827,807
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MULTI-LAYER REGISTRATION AND DIMENSIONAL TEST MARK FOR SCATTEROMETRICAL MEASUREMENT
App. No. 11/768,725
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INTEGRATED CIRCUIT WITH METAL SILICIDE REGIONS
App. No. 11/821,396
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INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
App. No. 11/811,519
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FABRICATION METHOD
App. No. 11/809,873
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STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
App. No. 11/809,686
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GUARD RING FOR IMPROVED MATCHING
App. No. 11/748,569
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DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT
App. No. 11/738,050
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MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
App. No. 11/733,673
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Planarization with reduced dishing
App. No. 11/695,169
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METHOD TO REDUCE BORON PENETRATION IN A SIGE BIPOLAR DEVICE
App. No. 11/694,021
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SYSTEMS AND METHODS FOR SUPPORTING A SUBSET OF MULTIPLE INTERFACE TYPES IN A SEMICONDUCTOR DEVICE
App. No. 11/684,674
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METHOD TO IMPROVE WRITER LEAKAGE IN A SIGE BIPOLAR DEVICE
App. No. 11/673,645
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PROCESS FOR MAKING AN ON-CHIP VACUUM TUBE DEVICE
App. No. 11/649,197
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III-V POWER FIELD EFFECT TRANSISTORS
App. No. 11/641,507
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METHOD AND APPARATUS FOR PERFORMING METALIZATION IN AN INTEGRATED CIRCUIT PROCESS
App. No. 11/609,509
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PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
App. No. 11/542,864
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METHOD OF ELECTRICAL TESTING OF AN INTERGRATED CIRCUIT WITH AN ELECTRICAL PROBE
App. No. 11/540,056
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LOW MUTUAL INDUCTANCE MATCHED INDUCTORS
App. No. 11/534,340
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APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
App. No. 11/524,107
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BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE
App. No. 11/531,477
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SYSTEMS AND METHODS FOR DISTRIBUTING I/O IN A SEMICONDUCTOR DEVICE
App. No. 11/530,550
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METHOD TO IMPROVE PERFORMANCE OF A BIPOLAR DEVICE USING AN AMORPHIZING IMPLANT
App. No. 11/469,032
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BIPOLAR JUNCTION TRANSISTOR HAVING A HIGH GERMANIUM CONCENTRATION IN A SILICON-GERMANIUM LAYER AND A METHOD FOR FORMING THE BIPOLAR JUNCTION TRANSISTOR
App. No. 10/598,213
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INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
App. No. 11/494,221
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METHOD FOR FORMING MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS
App. No. 11/458,270
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OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
App. No. 11/473,627
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A METHOD OF FORMING A SPIRAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE
App. No. 11/419,252
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A VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
App. No. 11/419,356
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DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
App. No. 11/418,873
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Adjustable Transmission Phase Shift Mask
App. No. 11/381,409
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INDUCTOR FORMED IN AN INTEGRATED CIRCUIT
App. No. 11/414,902
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Method to improve the control of electro-polishing by use of a plating electrode in an electrolyte bath
App. No. 11/409,377
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WAFER CHUCKING APPARATUS FOR SPIN PROCESSOR
App. No. 11/403,137
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INTERDIGITATED MESH TO PROVIDE DISTRIBUTED, HIGH QUALITY FACTOR CAPACITIVE COUPLING
App. No. 11/397,252
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High-density inter-die interconnect structure
App. No. 11/392,375
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INCORPORATING DOPANTS TO ENHANCE THE DIELECTRIC PROPERTIES OF METAL SILICATES
App. No. 11/389,643
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