Device and method to eliminate shorting induced by via to metal misalignment
View Patent ↗The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.
1. A semiconductor device interconnect, comprising:
a metal line located over a substrate;
a dielectric layer located over said metal line; and
an interconnect located in an opening in said dielectric layer, said opening including a landed portion located over said metal line and an unlanded portion located along at least a portion of a lateral edge of said metal line, said unlanded portion being at least partially filled with a polymer, and said landed portion being substantially free of said polymer, including sidewalls of said opening, and substantially filled with a conductive material, and wherein said dielectric layer contacts sidewalls of said metal line.
2. The semiconductor device interconnect as recited in claim 1 , wherein said dielectric layer includes voids.
3. The semiconductor device interconnect as recited in claim 2 , wherein said unlanded portion is adjacent to and intersects with at least one of said voids.
4. The integrated circuit as recited in claim 3 , wherein said polymer blocks entry of said conductive material into said at least one intersecting void.
5. The semiconductor device interconnect as recited in claim 2 , wherein said dielectric layer comprises silicon dioxide.
6. The semiconductor device interconnect as recited in claim 1 , wherein said polymer is a hydrocarbon chain containing fluorine.
7. The semiconductor device interconnect as recited in claim 1 , wherein said interconnect is a via.
8. The semiconductor device interconnect as recited in claim 1 , wherein said metal line is a first metal line and said semiconductor device interconnect further includes a second metal line wherein said first and second metal lines are spaced apart by a distance of about 0.22 microns and each has a width of about 0.22 microns and a height of about 680 nm.
9. The semiconductor device interconnect as recited in claim 1 , wherein said conductive material is a metal.
10. An integrated circuit comprising:
active devices located over a semiconductor substrate;
dielectric layers located over said active devices;
metal lines located over said active devices; and
interconnects located in openings in said dielectric layers, wherein at least one of said interconnect openings includes a landed portion located over one of said metal lines and an unlanded portion located along at least a portion of a lateral edge of said at least one of said metal lines, said unlanded portion being at least partially filled with a polymer and said landed portion being substantially filled with a conductive material, being substantially free of said polymer, including sidewalls of said interconnect openings, and substantially filled with a conductive material, said interconnects interconnecting said active devices, and wherein said dielectric layer contacts sidewalls of said metal lines.
11. The integrated circuit as recited in claim 10 , wherein said dielectric layers includes voids.
12. The integrated circuit as recited in claim 11 , wherein said unlanded portion is adjacent to and intersects with at least one of said voids.
13. The integrated circuit as recited in claim 10 , wherein said polymer is a hydrocarbon chain containing fluorine.
14. The integrated circuit as recited in claim 10 , wherein said interconnect is a via that is filled with a conductive metal.