IP Library Granted Patent US 7,449,388
Granted Patent B2
US 7,449,388 · App. 11/458,270 · Granted Nov 11, 2008

Method for forming multiple doping level bipolar junctions transistors

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Quick Facts
Patent No.
US 7,449,388
App. No.
11/458,270
Granted
Nov 11, 2008
Kind
B2
Abstract

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Claims (17)

1. A process for forming a bipolar junction transistor in a semiconductor substrate, the process comprising:

forming first doped tub regions of a first dopant type within the substrate, wherein the first doped tub regions are located within metal oxide semiconductor field effect transistor (MOSFET) regions;

using a first mask to form sinker regions of a second dopant type within the substrate, wherein at least a portion of the sinker regions are located within bipolar junction transistor (BJT) regions and a remaining portion of the sinker regions are located in the MOSFET regions adjacent the first doped tub regions;

using a second mask, and the second dopant type, to form first subcollectors within a portion of the BJT regions that include a portion of the sinker regions, and triple well regions within the MOSFET that electrically isolate the first doped tub regions, and the another mask covering a remaining portion of the sinker regions to prevent the remaining portion from being doped; and

forming gate structures over the MOSFET regions;

using a third mask to dope a portion of each of the first subcollectors, the remaining portions of the sinker regions, and source/drains regions in the first doped tub regions with the second dopant type; and

using a fourth mask to dope the remaining portions of the sinker regions to form second subcollectors and a portion of the first subcollector regions with the second dopant, such that the portion of the first subcollector regions has a dopant concentration different from a remaining portion of the first subcollector regions and the second subcollector regions.

2. The process of claim 1

wherein the first doped tub regions and the triple well regions and the gate structures cooperate to form a metal oxide semiconductor field effect transistors; and

forming second structures associated with the doped sinker region and the subcollector region, wherein the second structures, the doped sinker region and the subcollector region cooperate to form the bipolar junction transistor.

3. The process of claim 2 wherein the gate structures are formed after concurrently forming the first subcollector regions and the triple well regions.

4. The process of claim 2 further comprising forming second metal oxide semiconductor field effect transistors of an opposite doping type from the first metal oxide semiconductor field effect transistors, wherein the first and the second metal oxide semiconductor field effect transistors form complimentary metal oxide semiconductor field effect transistors.

5. The process of claim 1 wherein the step of forming the first subcollector regions and the triple well regions comprises implanting dopants to form the subcollector region and the triple well region.

6. The process of claim 5 wherein the step of implanting dopants further comprises implanting phosphorous at about 1000 keV with a dose of about 2E13 per cubic cm.

7. The process of claim 1 further comprising forming material layers overlying the substrate and forming an emitter windows within one or more of the material layers, wherein the step of doping the portion of the subcollector region comprises doping the portion of the subcollector region through the emitter window.

8. The method of claim 7 , further comprising forming a base in one or more of the BJT regions.

9. The method of claim 8 wherein at least three of the BJT's have different breakdown characteristics during operation.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2006
From: KERR, DANIE C.; CARROLL, MICHAEL S.; HAMAD, AMAL MA; LAI, THIET THE; KEY, ROGER W.
To: AGERE SYSTEMS INC.
Reel/Frame 017953/0024 →