IP Library Granted Patent US 7,763,414
Granted Patent B2
US 7,763,414 · App. 12/204,290 · Granted Jul 27, 2010

Pseudo low volume reticle (PLVR) design for ASIC manufacturing

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Quick Facts
Patent No.
US 7,763,414
App. No.
12/204,290
Granted
Jul 27, 2010
Kind
B2
Abstract

A Pseudo Low Volume Reticle (PLVR) which consists of multiple design layers on a single reticle. Specifically, the reticle can include two instances of each layer in order to facilitate die-to-die inspection techniques. A scribe is wrapped around each instance of the layer, such that both the frame and active area of the chip can be inspected with the die-to-die method. The chip consists of design data for a given part. The scribe, or frame, is preferably standard data across products which is used for yield and in line testing during the chip manufacturing process. Since only one chip and scribe unit is necessary to manufacture a device at each layer, it is only necessary that one chip and scribe instance yield during the reticle manufacturing process.

Claims (14)

1. A method of using a reticle to expose die onto a wafer, said method comprising:

providing the reticle, wherein the reticle comprises a plurality of sets of mask patterns, wherein each set comprises a plurality of mask patterns, wherein each mask pattern in a set of mask patterns is identical to each other, but is different from the mask patterns in the other at least one set of mask patterns; and

blading off at least one of the mask patterns on the reticle while using the reticle to expose at least one other mask pattern onto the wafer.

2. A method as recited in claim 1 , further comprising providing that the reticle comprises a first set of a plurality of mask patterns, wherein each mask pattern in the first set is identical to each other, and comprising a second set of a plurality of mask patterns, wherein each mask pattern in the second set is identical to each other, wherein each mask pattern in the first set is different than each mask pattern in the second set, and each mask pattern in the second set is different than each mask pattern in the first set.

3. A method as recited in claim 1 , further comprising providing that the reticle includes two instances of each of the mask patterns.

4. A method as recited in claim 1 , further comprising providing that the reticle includes a vertical scribe and a horizontal scribe proximate at least one of the mask patterns.

5. A method as recited in claim 1 , further comprising providing that the reticle includes a vertical scribe and a horizontal scribe proximate each of the mask patterns.

6. A method of using a reticle to expose die onto a wafer, said method comprising:

providing the reticle, wherein the reticle comprises a plurality of sets of mask patterns, wherein each set comprises a plurality of mask patterns, wherein each mask pattern in a set of mask patterns is identical to each other, but is different from the mask patterns in the other at least one set of mask patterns;

determining whether there is a defective mask pattern on the reticle, and blading off the defective mask pattern on the reticle while using the reticle to expose at least one other non-defective mask pattern onto the wafer.

7. A method as recited in claim 6 , further comprising providing that the reticle comprises a first set of a plurality of mask patterns, wherein each mask pattern in the first set is identical to each other, and comprising a second set of a plurality of mask patterns, wherein each mask pattern in the second set is identical to each other, wherein each mask pattern in the first set is different than each mask pattern in the second set, and each mask pattern in the second set is different than each mask pattern in the first set.

8. A method as recited in claim 6 , further comprising providing that the reticle includes two instances of each of the mask patterns.

9. A method as recited in claim 6 , further comprising providing that the reticle includes a vertical scribe and a horizontal scribe proximate at least one of the mask patterns.

10. A method as recited in claim 6 , further comprising providing that the reticle includes a vertical scribe and a horizontal scribe proximate each of the mask patterns.

Assignments (8)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →