Method to reduce trench capacitor leakage for random access memory device
A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material.
1. A method of manufacturing an integrated circuit, comprising:
forming first trench isolation structures in a transistor region of a semiconductor substrate;
forming second trench isolation structures in a dynamic random memory (DRAM) region of the semiconductor substrate;
forming an etch mask over the transistor region and the DRAM region;
patterning the etch mask over the second trench isolation structures to expose a portion of each of the second trench isolation structures with the transistor region remaining protected by the etch mask;
removing a portion of the exposed portions to form a gate trench in each of the second trench isolation structures, wherein each of the gate trenches include a first corner formed by the semiconductor substrate and a second corner formed by the trench isolation structure;
removing the etch mask from the DRAM region;
rounding at least the first corner of each of the gate trenches;
forming an oxide layer over a sidewall, the first rounded corner, and the semiconductor substrate adjacent each of the gate trenches;
forming a gate oxide over the semiconductor substrate in the transistor region;
filling each of the gate trenches with a gate material, the gate material extending over at least the first rounded corner and onto the semiconductor substrate adjacent each of the gate trenches;
forming the gate material over the transistor region;
patterning the gate material in the DRAM region and the transistor region to form gates; and
forming source/drains adjacent the gates.
2. The method recited in claim 1 , wherein a radius of curvature of the first corner is less than a radius of curvature of the first rounded corner.
3. The method recited in claim 1 , wherein the semiconductor device is a dynamic random access memory device and wherein filling the gate trench forms a trench capacitor and the method further includes forming a gate electrode adjacent the trench capacitor.
4. The method recited in claim 1 , wherein rounding the first corners further includes rounding the second corner and filling extending the gate material over the second rounded corner.
5. The method recited in claim 4 , wherein rounding the first and second corners includes using a sputter process that includes using a gas flowed at about 100 seem to about 300 seem, at a power from about 200 to about 500 watts and at a pressure ranging from about 150 to about 350 milliTorr.
6. The method recited in claim 5 , wherein the gas is argon.
7. The method recited in claim 1 , wherein forming an oxide layer includes growing an oxide layer from the surface of the sidewall, the first rounded corner, and the semiconductor substrate.
8. The method recited in claim 7 , wherein the oxide layer has a thickness that ranges from about 2 nm to about 3 nm and has a thickness uniformity that varies by less than about 0.2 nm.
9. The method recited in claim 7 , wherein growing the oxide layer includes flowing oxygen at a rate ranging from about 7 liters per second to about 10 liters per second and at a temperature ranging from about 1000° C. to about 1100° C.
10. The method recited in claim 1 , wherein removing the etch mask from the DRAM region includes removing nitride and oxide layers.