Guard ring for improved matching
View Patent ↗A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.
1. During fabrication of an integrated circuit on a semiconductor wafer, a method for reducing photoresist thickness variation over a first specified area of a patterned circuit on the wafer comprising the steps of:
a. forming a first leveling guard ring wall around a first specified area of a semiconductor wafer defining an interior area; and
b. applying photoresist within the first leveling guard ring wall and over the first specified area in said interior area, wherein said photoresist substantially fills an unoccupied volume within said guard ring wall in said interior area.
2. The method of claim 1 additionally comprising fabricating one or more devices in the first specified area.
3. The method of claim 1 additionally comprising fabricating in the first specified area an array of two or more devices in a common centroid pattern.
4. The method of claim 1 forming the first leveling guard ring wall to a height sufficient to reduce the effect of surrounding features' elevations on uniformity of photoresist thickness within the first specified area.
5. The method of claim 4 wherein the height is substantially equal to a height of photoresist-flow-disturbing components on the patterned circuit.
6. The method of claim 1 additionally comprising adding interconnecting features through the first leveling guard ring wall.
7. The method of claim 1 additionally comprising adding interconnecting features over the first leveling guard ring wall.
8. The method of claim 1 , additionally comprising forming at least one additional leveling guard ring wall around, respectively, at least one additional specified area, and fabricating in each of the at least one additional specified area(s) an array of two or more devices.
9. The method of claim 3 , additionally comprising forming at least one additional leveling guard ring wall around, respectively, at least one additional specified area, and fabricating in each of the at least one additional specified area(s) an array of two or more devices in a common centroid pattern.
10. A method of fabrication for a semiconductor wafer comprising:
a. designing an arrangement of integrated circuit features including features within a first specified area;
b. forming a first leveling guard ring wall around the first specified area defining an interior area;
c. applying a photoresist layer within the first leveling guard ring wall and over the features within the first specified area in said interior area, wherein said photoresist substantially fills an unoccupied volume within said guard ring wall in said interior area; and
d. imaging the photoresist layer to define features within the first specified area in said interior area.
11. The method of claim 10 , designing features within the first specified area in a common centroid pattern.
12. The method of claim 10 , the designing additionally comprising determining a location for the leveling guard ring wall based on analysis of elevations of features local to the first specified area, the analysis lessening the effects of the elevations on variation in thickness of the photoresist layer.
13. The method of claim 10 , additionally comprising forming at least one additional leveling guard ring wall around an additional specified area comprising features within.
14. The method of claim 13 , additionally designing the features within the additional specified area in a common centroid pattern.
15. During fabrication of an integrated circuit on a semiconductor wafer, a method for reducing photoresist thickness variation comprising the steps of:
a. forming a leveling guard ring wall around a specified area, the guard ring wall comprising an array of features formed around the specified area defining an interior area; and
b. applying photoresist within the leveling guard ring wall and over the specified area, wherein said photoresist substantially fills an unoccupied volume within said guard ring wall in said interior area;
wherein the guard ring wall reduces photoresist thickness variation within the specified area.
16. The method of claim 15 wherein the array of features formed around the specified area is comprised of devices selected from the group consisting of transistors, resistors, capacitors, and diodes.
17. The method of claim 15 additionally comprising fabricating one or more devices in the first specified area.
18. The method of claim 15 additionally comprising fabricating in the first specified area an array of two or more devices in a common centroid pattern.
19. The method of claim 15 , additionally comprising designing the integrated circuit to comprise a plurality of specified areas globally spaced across the integrated circuit.