Programmable nanotube interconnect
View Patent ↗Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.
1. A method comprising:
forming a transistor layer directly above a semiconductor substrate, with an entire surface of the transistor layer directly contacting an entire surface of the semiconductor substrate;
forming a metal layer above the semiconductor substrate and directly above the transistor layer, with an entire surface of the metal layer directly contacting another entire surface of the transistor layer;
patterning a programmable interconnect layer within at least one of the metal layer and the semiconductor substrate to determine power allocation in a voltage region of the transistor layer, the programmable interconnect layer having a carbon nanotube structure configured to function as a switch based on a current applied thereto; and
enabling formation of a route in the metal layer through the programmable interconnect layer through applying the current to the carbon nanotube structure.
2. The method of claim 1 , further comprising stacking at least two of the programmable interconnect layers adjacent to each other.
3. The method of claim 2 , further comprising coupling at least two of the programmable interconnect layers through a vertical via.
4. The method of claim 1 , further comprising utilizing the programmable interconnect layer as a pass gate and a memory element in the metal layer.
5. The method of claim 1 , further comprising configuring the route based on an algorithm that considers an activity in the voltage region and other voltage regions of an integrated circuit.
6. An integrated circuit comprising:
a semiconductor substrate;
a transistor layer formed directly above the semiconductor substrate, with an entire surface of the transistor layer directly contacting an entire surface of the semiconductor substrate, the transistor layer having a plurality of voltage regions;
a metal layer formed above the semiconductor substrate and directly above the transistor layer, with an entire surface of the metal layer directly contacting another entire surface of the transistor layer; and
a programmable interconnect layer patterned within at least one of the metal layer and the semiconductor substrate to determine power allocation in a voltage region of the transistor layer, the programmable interconnect layer having a carbon nanotube structure such that a current applied thereto enables formation of a route in the metal layer, and the carbon nanotube structure having a switch functionality associated therewith based on the current applied thereto.
7. The integrated circuit of claim 6 , wherein the programmable interconnect layer includes a trench of electrodes, the carbon nanotube structure being sputtered across the trench, and a planar via coupled to a communication line associated with the carbon nanotube structure.
8. The integrated circuit of claim 6 , wherein the programmable interconnect layer is configured to function as a pass gate and a memory element in the metal layer.
9. The integrated circuit of claim 8 , wherein the plurality of the programmable interconnect layers further comprises:
an upper interconnect layer having a plurality of upper nanotube switches oriented in a horizontal communication line; and
a lower interconnect layer having a plurality of lower nanotube switches oriented in a vertical communication line.
10. The integrated circuit of claim 9 , further comprising a plurality of vias to communicatively couple to the horizontal communication line and the vertical communication line and to provide a buffer space between the upper interconnect layer and the lower interconnect layer.
11. The integrated circuit of claim 9 , wherein a vertical via is configured to couple at least two of the programmable interconnect layers.
12. The integrated circuit of claim 9 , wherein the upper nanotube switches and the lower nanotube switches are programmable based on an algorithm applied by a data processing system associated with the integrated circuit incorporating the upper interconnect layer and the lower interconnect layer.
13. The integrated circuit of claim 9 , wherein the plurality of upper nanotube switches and the plurality of lower nanotube switches are associated with the voltage region in the transistor layer of the integrated circuit.
14. The integrated circuit of claim 13 , wherein a utilization rate of the voltage region is monitored on a periodic interval by the integrated circuit, such that the algorithm is processed when the utilization rate drops below a minimum threshold.
15. A microelectronic structure comprising:
a transistor layer formed directly above a semiconductor substrate, with an entire surface of the transistor layer directly contacting an entire surface of the semiconductor substrate;
a metal layer formed above the semiconductor substrate and directly above the transistor layer, with an entire surface of the metal layer directly contacting another entire surface of the transistor layer; and
a programmable interconnect layer patterned within at least one of the metal layer and the semiconductor substrate to determine power allocation in a voltage region of the transistor layer, the programmable interconnect layer having a carbon nanotube structure such that a current applied thereto enables formation of a route in the metal layer, and the carbon nanotube structure having a switch functionality associated therewith based on the current applied thereto.
16. The structure of claim 15 ,
wherein the programmable interconnect layer includes a trench of electrodes, the carbon nanotube structure being sputtered across the trench, and a planar via coupled to a communication line associated with the carbon nanotube structure.
17. The structure of claim 15 , wherein at least two of the programmable interconnect layers are stacked adjacent to each other.
18. The structure of claim 17 , wherein a vertical via is configured to couple at least two of the programmable interconnect layers.
19. The structure of claim 15 , wherein the programmable interconnect layer is configured to function as a pass gate and a memory element in the metal layer.
20. The structure of claim 15 , wherein a configuration of the route is performed based on an algorithm that considers activity in the voltage region and other voltage regions of an integrated circuit including the microelectronic structure.