IP Library Granted Patent US 7,646,077
Granted Patent B2
US 7,646,077 · App. 12/191,171 · Granted Jan 12, 2010

Methods and structure for forming copper barrier layers integral with semiconductor substrates structures

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 7,646,077
App. No.
12/191,171
Granted
Jan 12, 2010
Kind
B2
Abstract

The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

Claims (29)

1. A semiconductor structure, comprising:

a semiconductor substrate having copper interconnect structures formed thereon;

an overlying insulating layer being formed of a material that includes at least one of silicon and carbon, the insulating layer having an opening that exposes the copper interconnect structures;

an inner surface of the opening including a dielectric copper barrier layer formed integrally with and from the material of the insulating layer using a plasma process sufficient to alter the diffusion behavior of the material of the insulating material to increase its resistance to copper diffusion, thereby preventing the diffusion of copper into the insulating layer; and

a copper plug filling the opening.

2. A semiconductor structure as in claim 1 wherein the overlying insulating layer is formed of a low-K dielectric material.

3. A semiconductor structure as in claim 2 wherein the low-K dielectric material is an organo-silicate glass material.

4. A semiconductor structure as in claim 1 wherein the dielectric copper barrier layer formed on the inner surface of the opening is formed of densified insulating layer material forming part of the insulating layer.

5. A semiconductor structure as recited in claim 1 wherein the insulating layer comprises ortho-silicate glass material and wherein the integrally formed dielectric copper barrier layer is comprises densified ortho-silicate glass material.

6. A semiconductor structure as recited in claim 5 wherein the densified ortho-silicate glass material of the dielectric copper barrier layer is densified to a density of greater than about 2 grams per cubic centimeter.

7. A semiconductor structure as recited in claim 1 wherein the integrally formed dielectric copper barrier layer is in the range of about 10 Å to about 200 Å thick.

8. semiconductor structure as recited in claim 7 wherein the dielectric copper barrier layer comprises densified insulating layer material.

9. A semiconductor structure as recited in claim 8 wherein the insulating layer comprises carbon and oxygen materials and wherein the densified dielectric copper barrier layer has reduced oxygen concentration relative to the underlying insulating layer.

10. A semiconductor structure as recited in claim 8 wherein the dielectric copper barrier layer has an increased concentration of silicon carbide relative to the underlying insulating layer.

11. A semiconductor structure as recited in claim 8 wherein the dielectric copper barrier layer has an increased concentration of silicon carbon nitride relative to the underlying insulating layer.

12. A semiconductor structure as recited in claim 1 wherein the insulating layer comprises carbon and oxygen materials and wherein the dielectric copper barrier layer treated by plasma process has reduced oxygen concentration relative to the underlying insulating layer.

13. A semiconductor structure as recited in claim 12 wherein the dielectric copper barrier layer treated by plasma process has an increased concentration of silicon carbide relative to the underlying insulating layer.

14. A semiconductor structure as recited in claim 1 wherein the dielectric copper barrier layer treated by plasma process has an increased concentration of silicon carbon nitride relative to the underlying insulating layer.

15. A method for forming a copper interconnect having a dielectric copper barrier layer, the method comprising:

providing a substrate having formed thereon copper interconnect structures and an insulating layer that overlies the copper interconnect structures, the insulating layer having an opening that exposes an underlying copper interconnect structure and is configured to receive an inlaid conducting structure that is in electrical contact with the copper interconnect structure, the insulating layer being formed of a low-K dielectric material that includes at least one of silicon and carbon material;

plasma treating a surface portion of the insulating layer so that a dielectric copper barrier layer is formed on an upper surface portion of the inside surface of the opening thereby producing a barrier to copper diffusion into the insulating layer; and

filling the opening with a copper material.

16. A method as recited in claim 15 wherein plasma treating the surface of the insulating layer densifies the upper surface portion of the insulating layer forming the dielectric copper barrier layer from said densified insulating layer material.

17. A method as recited in claim 16 wherein the insulating layer comprises ortho-silicate glass material and wherein plasma treating the surface of the insulating layer generates a dielectric copper barrier layer comprising densified ortho-silicate glass material.

18. A method as recited in claim 16 wherein the plasma treating generates a densified ortho-silicate glass containing dielectric copper barrier layer having a density of greater than about 2 grams per cubic centimeter.

19. A method as recited in claim 15 wherein plasma treating the surface of the insulating layer forms the dielectric copper barrier layer in the range of about 10 Å to about 200 Å thick.

20. A method as recited in claim 19 wherein the insulating layer comprises carbon and oxygen materials and wherein plasma treating the surface of the insulating layer to form the dielectric copper barrier layer reduces an oxygen concentration in the dielectric copper barrier layer relative to the underlying insulating layer.

21. A method as recited in claim 19 wherein the insulating layer comprises silicon, carbon, and oxygen materials and wherein plasma treating the surface of the insulating layer to form the dielectric copper barrier layer increases a concentration of silicon carbide in the dielectric copper barrier layer relative to the underlying insulating layer.

22. A method as recited in claim 15 wherein plasma treating the surface of the insulating layer to form the dielectric copper barrier layer increases a concentration of silicon carbon nitride in the dielectric copper barrier layer relative to the underlying insulating layer.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (3)
Division 1113100300 · May 16, 2005
Division 1032193800 · Dec 16, 2002
Related Publication 20080303155A1 · Dec 11, 2008