Interdigitated mesh to provide distributed, high quality factor capacitive coupling
View Patent ↗Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom; and a second metal line electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers capacitively coupled. The basic structure of metal lines with interlocking metal fingers may be repeated on multiple adjacent metallization layers, with the metal lines oriented either in parallel or perpendicular.
1. An integrated circuit device structure comprising:
a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom, the first metal line being significantly thicker along a direction of extension of the first set of metal fingers than each of the first set of metal fingers along a direction perpendicular to the extension thereof;
a second metal line implemented on the metallization layer, the second metal line being electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers being capacitively coupled, and the second metal line also being significantly thicker along a direction of extension of the second set of metal fingers than each of the second set of metal fingers along a direction perpendicular to the extension thereof; and
a via array provided respectively on the first metal line and the second metal line to enable coupling of the metallization layer to another metallization layer in a direction perpendicular to a plane including the first metal line, wherein the via array is only at one end portion of the first metal line and the second metal line, respectively, the first set of metal fingers, the second metal line and the second set of metal fingers.
2. The structure of claim 1 , wherein the first metal line is a ground wire of a power mesh of an integrated circuit device and the second metal line is a voltage wire of the power mesh.
3. The structure of claim 1 , wherein the first metal line and the second metal line are configured to operate as two different voltage nodes of an integrated circuit device.
4. The structure of claim 1 , wherein a distance between the first metal line and the second metal line is approximately 5 microns.
5. The structure of claim 1 , wherein a metal finger of the first set of metal fingers is approximately 0.5 microns from a corresponding metal finger of the second set of metal fingers.
6. The structure of claim 1 , wherein the first set of metal fingers and the second set of metal fingers include a number of metal fingers determined based upon a required grid resistance, desired capacitance, quality factor, metal density for the metallization layer, and defect density for the metallization layer.
7. The structure of claim 1 , further comprising:
a second metallization layer formed adjacent to the first metallization layer with a dielectric layer disposed between the first metallization layer and the second metallization layer; and
a first metal line with corresponding metal fingers and a second metal line with corresponding metal fingers on the second metallization layer, with the first and second metal lines on the second metallization layer in a perpendicular orientation to the first and second metal lines on the first metallization layer, and the first and second sets of metal fingers on the first and second metallization layers in a perpendicular orientation,
wherein the first metallization layer and the second metallization layer are coupled through the via array.
8. A method comprising:
forming a first metal line implemented on a first metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom, the first metal line being significantly thicker along a direction of extension of the first set of metal fingers than each of the first set of metal fingers along a direction perpendicular to the extension thereof;
forming a second metal line implemented on the metallization layer, the second metal line being electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers being capacitively coupled, and the second metal line also being significantly thicker along a direction of extension of the second set of metal fingers than each of the second set of metal fingers along a direction perpendicular to the extension thereof; and
providing a via array respectively on the first metal line and the second metal line, wherein the via array is only at one end portion of the first metal line and the second metal line, respectively, to enable coupling of the metallization layer to another metallization layer in a direction perpendicular to a plane including the first metal line, the first set of metal fingers, the second metal line and the second set of metal fingers.
9. The method of claim 8 , wherein the first metal line is a ground wire of a power mesh of an integrated circuit device and the second metal line is a voltage wire of the power mesh.
10. The method of claim 8 , wherein the first metal line and the second metal line are configured to operate as two different voltage nodes of an integrated circuit device.
11. The method of claim 8 , wherein the first set of metal fingers and the second set of metal fingers interlock.
12. The method of claim 8 , wherein a distance between the first metal line and the second metal line is approximately 5 microns.
13. The method of claim 8 , wherein a metal finger of the first set of metal fingers is approximately 0.5 microns from a corresponding metal finger of the second set of metal fingers.
14. The method of claim 8 , wherein the first set of metal fingers and the second set of metal fingers include a number of metal fingers determined based upon a required grid resistance, desired capacitance, quality factor, metal density for the metallization layer, and defect density for the metallization layer.
15. The method of claim 8 , further comprising:
forming a second metallization layer adjacent to the first metallization layer with a dielectric layer disposed between the first metallization layer and the second metallization layer; and
forming a first metal line with corresponding metal fingers and a second metal line with corresponding metal fingers on the second metallization layer, with the first and second metal lines on the second metallization layer in a perpendicular orientation to the first and second metal lines on the first metallization layer, and the first and second sets of metal fingers on the first and second metallization layers in a perpendicular orientation; and
coupling the first metallization layer and the second metallization layer through the via array.
16. An integrated circuit device comprising:
a semiconductor substrate having formed thereon a plurality of transistors; and
a power mesh for distributing power to the transistors, the power mesh including a plurality of first metal lines that are ground wires and a plurality of second metal lines that are voltage wires alternately formed on a metallization layer of the semiconductor substrate, each ground wire and each voltage wire being electrically isolated, each ground wire having a first set of metal fingers extending therefrom and each voltage wire having a second set metal fingers extending therefrom, each of the plurality of first metal lines being significantly thicker along a direction of extension of the first set of metal fingers than each of the first set of metal fingers along a direction perpendicular to the extension thereof, each of the plurality of second metal lines also being significantly thicker along a direction of extension of the second set of metal fingers than each of the second set of metal fingers along a direction perpendicular to the extension thereof, the first set of metal fingers and the second set of metal fingers being capacitively coupled, thereby increasing the bypass capacitance of the power mesh, and the power mesh further comprising a via array provided respectively on each of the plurality of first metal lines and each of the plurality of second metal lines, wherein the via array is only at one end portion of each of the plurality of first metal lines and each of the plurality of second metal lines, respectively, to enable coupling of the metallization layer to another metallization layer in a direction perpendicular to a plane including the plurality of first metal lines, the first set of metal fingers, the plurality of second metal lines and the second set of metal fingers.
17. The integrated circuit device of claim 16 , wherein the first set of metal fingers and the second set of metal fingers interlock.
18. The integrated circuit device of claim 16 , wherein a distance between the each of the plurality of first metal lines and each of the plurality of second metal lines is approximately 5 microns.
19. The integrated circuit device of claim 18 , wherein a metal finger of the first set of metal fingers is approximately 0.5 microns from a corresponding metal finger of the second set of metal fingers.
20. The integrated circuit device of claim 16 , wherein the first set of metal fingers and the second set of metal fingers include a number of metal fingers determined based upon a required grid resistance, desired capacitance, quality factor, metal density for the metallization layer, and defect density for the metallization layer.
21. The integrated circuit device of claim 16 , further comprising:
a second metallization layer formed adjacent to the first metallization layer with a dielectric layer disposed between the first metallization layer and the second metallization layer; and
a first metal line with corresponding metal fingers and a second metal line with corresponding metal fingers on the second metallization layer, with the first and second metal lines on the second metallization layer in a perpendicular orientation to the first and second metal lines on the first metallization layer, and the first and second sets of metal fingers on the first and second metallization layers in a perpendicular orientation,
wherein the first metallization layer and the second metallization layer are coupled through the via array.