Method and system for reducing inter-layer capacitance in integrated circuits
View Patent ↗The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
1. A system for intelligent placement of dummy fill patterns in an integrated circuit fabrication process, comprising:
means for obtaining layout information of the integrated circuit, the integrated circuit including a plurality of layers;
means for selecting a first layer and a second layer, wherein the second layer is placed successively to the first layer;
means for obtaining initial layouts of metal lines on the first layer and the second layer;
means for determining a first dummy fill space based on the initial layout on the first layer, the first dummy fill space suitable for including a plurality of dummy fill features on the first layer;
means for determining a second dummy fill space based on the initial layout on the second layer, the second dummy fill space suitable for including a plurality of dummy fill features on the second layer;
means for determining an overlap between the first dummy fill space and the second dummy fill space; and
means for minimizing the overlap by arranging the plurality of first dummy fill features and the plurality of second dummy fill features,
wherein the integrated circuit includes the first layer and the second layer.
2. The system as described in claim 1 , the means for minimizing the overlap further comprising:
means for determining whether a dummy fill pattern of the first layer is a checkerboard pattern; and
means for placing the plurality of first dummy fill features to form the checkerboard pattern if the dummy fill pattern of the first layer is not arranged in the checkerboard pattern.
3. The system as described in claim 1 , further comprising:
means for placing the plurality of second dummy fill features based on the dummy fill pattern of the first layer if the dummy fill pattern of the first layer is already the checkerboard pattern.
4. The system as described in claim 3 , wherein the plurality of second dummy fill features are placed so as to form an alternate checkerboard pattern against the checkerboard pattern of the plurality of first dummy fill features.
5. The system as described in claim 3 , wherein the plurality of second dummy fill features are placed so as to be offset from the plurality of first dummy fill features.
6. The system as described in claim 1 , wherein a total bulk capacitance of the integrated circuit is minimized.