Yield profile manipulator
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
1. A processor-based method of creating a graphical profile map for integrated circuits on a substrate, the method comprising:
assembling into a processor-accessible memory die placement information for the integrated circuits on the substrate,
displaying the die placement information using the processor as die placement boundaries on a representation of the substrate,
assembling into the processor-accessible memory shot placement information for the integrated circuits on the substrate,
displaying the shot placement information using the processor as shot placement boundaries on the representation of the substrate,
assembling into the processor-accessible memory integrated circuit property information for the integrated circuits on the substrate, and
displaying the integrated circuit property information using the processor as contours on the representation of the substrate, where the contours are not limited to either of the die placement boundaries and the shot placement boundaries.
2. The method of claim 1 , wherein the step of assembling the integrated circuit property information comprises acquiring the integrated circuit property information from a database of historical integrated circuit property information when a desired amount of historical integrated circuit property information is available, and when the desired amount of historical integrated circuit property information is not available, generating additional integrated circuit property information with programmable algorithms operating on the available historical integrated circuit property information.
3. The method of claim 2 , wherein the programmable algorithms comprise modification algorithms and smoothing algorithms.
4. The method of claim 1 , wherein the integrated circuit property information is presented by representing different integrated circuit property information value ranges with different colors.
5. The method of claim 1 , further comprising a graphical indication depicting an offset from a center of the substrate to a center of a closest unit of the shot placement information.
6. A processor-based method of creating a graphical yield profile map for integrated circuits on a substrate, the method comprising:
assembling into a processor-accessible memory die grid information for the integrated circuits on the substrate,
displaying the die grid information using the processor as die grid boundaries on a representation of the substrate,
assembling into the processor-accessible memory shot grid information for the integrated circuits on the substrate,
displaying the shot grid information using the processor as shot grid boundaries on the representation of the substrate,
assembling into the processor-accessible memory yield information by location of the integrated circuits on the substrate, by acquiring the yield information from a database of historical yield information using the processor when a desired amount of historical yield information is available, and when the desired amount of historical yield information is not available, generating additional yield information with programmable algorithms using the processor operating on the available yield information,
displaying the yield information using the processor as contours on the representation of the substrate, where the contours are not limited to either of the die grid boundaries and the shot grid boundaries.
7. The method of claim 6 , wherein the programmable algorithms comprise modification algorithms and smoothing algorithms.
8. The method of claim 6 , wherein the yield information is presented by representing different yield value ranges with different colors.