TRANSISTOR FABRICATION METHOD
A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
1 . A method of semiconductor integrated circuit fabrication comprising:
forming a dielectric layer upon a substrate;
forming a conductive layer upon said dielectric layer;
forming a material layer overlying said conductive layer;
forming a patterned resist upon said material layer;
at least partially etching said material layer to thereby form a raised feature;
removing said resist;
using said raised feature as a mask, anisotropically etching said conductive layer and said dielectric layer, thereby forming a gate;
forming source and drain regions; and
removing said mask,
wherein said material layer is formed from the group consisting of BPSG and PSG.
2 - 7 . (canceled)
8 . The method of claim 1 , further including the steps of:
blanket depositing a refractory metal upon said gate and said source and drain region;
heating said refractory metal to form a silicide upon said gate and said source and drain region.
9 . The method of claim 1 further including the step of:
forming spacers adjacent said gate prior to formation of said source and drain regions.
10 . The method of claim 8 further including the step of:
forming spacers adjacent said gate prior to deposition of said refractory metal.
11 . The method of claim 1 or 9 further including the steps of:
prior to removal of said material layer, blanket depositing a refractory metal upon said material layer and upon said source and drain;
heating said refractory metal to form a silicide upon said source and drain and not upon said gate.
12 . The method of claim 1 or 9 further including the steps of:
forming a protective layer over said source and drain;
exposing said conductive layer of said gate by removing said material layer;
depositing a refractory metal upon said conductive layer and upon said protective layer;
heating said refractory metal to form silicide upon said gate and not upon said source and drain.
13 . The method of claim 1 or 9 further including the steps of:
forming a silicide layer between said conductive layer and said material layer prior to said step of forming a patterned resist.
14 . The method of claim 1 or 9 further including the steps, prior to removal of said material layer, of:
blanket depositing a refractory metal upon said gate and source and drain region;
reacting said refractory metal to form a silicide upon said source and drain region and not upon said gate.
15 - 23 . (canceled)
24 . The method of claim 1 , in which said material layer is formed from PSG having a doping of about 2% or greater phosphorus.
25 . The method of claim 1 , in which said material layer is formed from BPSG having about 2% boron and 4% phosphorus.