IP Library Granted Patent US 8,227,319
Granted Patent B2
US 8,227,319 · App. 12/728,412 · Granted Jul 24, 2012

Bipolar junction transistor having a high germanium concentration in a silicon-germanium layer and a method for forming the bipolar junction transistor

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 8,227,319
App. No.
12/728,412
Granted
Jul 24, 2012
Kind
B2
Abstract

A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Claims (34)

1. A method of manufacturing a semiconductor device comprising:

epitaxially growing a silicon-germanium base on a collector;

thermally oxidizing the base to preferentially grow silicon dioxide on an upper surface of the base to form a germanium-enriched region in an upper region of the base;

annealing the semiconductor device to redistribute germanium atoms of the germanium-enriched region;

removing the silicon dioxide; and

depositing an emitter overlying the base.

2. The method of claim 1 wherein the germanium-enriched region has a low level of lattice defects.

3. The method of claim 1 wherein prior to the step of thermally oxidizing, the silicon-germanium base comprises a graded doped silicon-germanium base or a stepped doped silicon-germanium base.

4. The method of claim 1 wherein prior to the step of thermally oxidizing, the silicon-germanium base comprises a uniformly doped silicon-germanium base.

5. The method of claim 1 wherein a concentration of germanium in the germanium-enriched region ranges from about 30 percent to about 75 percent relative to a concentration of silicon in the germanium-enriched region.

6. The method of claim 1 wherein the step of thermally oxidizing the base comprises thermally oxidizing the base within a temperature range of about 700 to about 900 degrees Celsius.

7. The method of claim 1 wherein the germanium-enriched region contacts with the emitter.

8. The method of claim 1 wherein a concentration of germanium in the germanium-enriched region decreases abruptly from a concentration in the upper region of the base in a direction toward the collector.

9. The method of claim 1 wherein the step of thermally oxidizing the base further comprises thermally oxidizing the base to preferentially grow silicon dioxide on an upper surface of the base to form the germanium-enriched region adjacent the silicon dioxide.

10. The method of claim 1 wherein the annealing step increases a germanium concentration in a region of the base proximate the germanium-enriched region.

11. The method of claim 1 wherein the silicon-germanium base comprises a silicon-germanium layer within a base.

12. The method of claim 1 wherein the annealing occurs after depositing the emitter.

13. A method of manufacturing a semiconductor device comprising:

forming a base on a silicon collector, wherein the base comprises a silicon-germanium layer proximate an upper surface thereof;

thermally oxidizing the silicon-germanium layer to form a germanium-enriched portion proximate the upper surface, wherein the germanium-enriched portion has a significantly greater germanium concentration than a remainder of the base;

annealing the semiconductor device to redistribute germanium atoms of the germanium-enriched portion; and

forming an emitter on the germanium-enriched portion.

14. The method of claim 13 wherein the germanium-enriched portion has a germanium concentration greater than about 30%.

15. The method of claim 13 wherein the annealing occurs after forming the emitter.

16. A method of manufacturing a semiconductor device comprising:

forming a silicon-germanium base region, having a first upper surface, over a collector region;

reacting the base region along the upper surface to form a thermally grown oxide in the first upper surface, and thereby to form a germanium-enriched portion proximate an upper surface of the base region;

removing the thermally grown oxide to expose a second upper surgace of the base region;

annealing the semiconductor device to redistribute germanium atoms of the germanium-enriched portion; and

forming an emitter region over the base.

17. The method of claim 16 wherein the step of reacting the base region further comprises varying a germanium concentration such that the germanium concentration is greater near the second upper surface.

18. The method of claim 17 wherein the germanium concentration near the second surface is between about 30 percent and about 75 percent relative to the concentration of silicon near the second surface.

19. The method of claim 16 wherein the step of reacting the base region further comprises reacting the base region within a temperature range of about 700 to about 900 degrees Celsius.

20. The method of claim 16 wherein the annealing occurs after forming the emitter region.

Assignments (9)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2010
From: GRIGLIONE, MICHELLE D.
To: AGERE SYSTEMS INC.
Reel/Frame 024113/0706 →
Continuity (3)
Division 10598213
Provisional Application 60552308 · Mar 10, 2004
Related Publication 20110230031A1 · Sep 22, 2011