Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
View Patent ↗A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.
1. A method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor in a semiconductor layer, comprising:
forming MOSFET structures in a MOSFET region of a semiconductor layer;
forming bipolar junction transistor structures, including an emitter material layer, in a bipolar junction transistor region of the semiconductor layer;
forming a first material layer over the emitter material layer;
forming a hardmask material layer of silicon dioxide over the emitter material layer and the first material layer;
patterning the hardmask material layer with a lithographic mask to form a patterned hardmask, comprising forming a photoresist layer over the hard mask layer, patterning the photoresist layer and patterning the hard mask layer according to a pattern in the photoresist layer;
using the patterned hardmask to pattern the emitter material layer and the first material layer during an etch process to form an emitter electrode of a bipolar transistor, comprising:
removing the photoresist layer;
etching the first material layer according to a pattern in the hard mask layer;
etching the emitter material layer according to the pattern in the hard mask layer; and
removing the hard mask layer; and
heating the semiconductor layer subsequent to forming the emitter electrode.
2. The method of claim 1 wherein forming first MOSFET structures in the MOSFET region further comprises:
forming an isolation region;
forming a doped tub region;
forming a gate stack overlying the tub region; and
forming lightly doped regions in the tub region.
3. The method of claim 1 wherein forming bipolar junction transistor structures comprises;
forming a bipolar junction transistor collector;
forming a bipolar junction transistor base; and
depositing an emitter polysilicon layer, wherein the emitter material layer comprises the emitter polysilicon layer.
4. The method of claim 1 wherein the MOSFET structures are first MOSFET structures that comprise a doped tub region and a gate stack, and wherein the method further includes forming second MOSFET structures comprising:
forming gate stack spacers adjacent the gate stack;
forming source/drain regions in the tub region; and
wherein heating comprises heating the semiconductor layer to activate dopants forming the source/drain regions.
5. The method of claim 1 further comprising removing unpatterned portions of the emitter material layer after the step of heating.
6. The method of claim 1 wherein the first material layer comprises a silicon oxynitride layer, a silicon nitride layer, a silicon carbide layer or a silicon dioxide layer.
7. The method of claim 1 wherein forming the first material layer comprises forming the first material layer to a thickness of ranging from about 30 to about 60 nm.
8. A method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor in a semiconductor layer, comprising:
forming MOSFET structures in a MOSFET region of a semiconductor layer;
forming bipolar junction transistor structures, including an emitter material layer, in a bipolar junction transistor region of the semiconductor layer;
forming a hardmask material layer over the emitter material layer;
patterning the hardmask material layer with a lithographic mask to form a patterned hardmask, wherein patterning the hard mask material layer comprises etching the first material layer according to a plasma etch process employing a fluorine-based material or etching the first material layer according to a plasma etch process employing C2F6 and oxygen;
using the patterned hardmask to pattern the emitter layer during an etch process to form an emitter electrode of a bipolar transistor; and
heating the semiconductor layer subsequent to forming the emitter electrode.
9. A method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor in a semiconductor layer, comprising:
forming MOSFET structures in a MOSFET region of a semiconductor layer;
forming bipolar junction transistor structures, including an emitter material layer, in a bipolar junction transistor region of the semiconductor layer;
forming a hardmask material layer over the emitter material layer;
patterning the hardmask material layer with a lithographic mask to form a patterned hardmask;
using the patterned hardmask to pattern the emitter layer during an etch process to form an emitter electrode of a bipolar transistor; and
heating the semiconductor layer subsequent to forming the emitter electrode, wherein the hardmask material layer limits out diffusion of dopants from the patterned emitter to other bipolar junction transistor structures during heating.