IP Library Granted Patent US 7,741,702
Granted Patent B2
US 7,741,702 · App. 11/927,978 · Granted Jun 22, 2010

Semiconductor structure formed using a sacrificial structure

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Quick Facts
Patent No.
US 7,741,702
App. No.
11/927,978
Granted
Jun 22, 2010
Kind
B2
Abstract

A semiconductor structure is provided which eliminates the contact resistance traditionally associated with a junction between one or more contacts and a buried conductive structure formed in the semiconductor structure. The semiconductor structure includes a first insulating layer formed on a semiconductor layer and a conductive structure formed on at least a portion of the first insulating layer. A second insulating layer is formed on at least a portion of the conductive structure. At least one contact is formed through the second insulating layer and electrically connected to the conductive structure. The contact and the conductive structure are formed as a substantially homogeneous structure in a same processing step.

Claims (42)

1. A semiconductor structure, comprising:

a first insulating layer formed on a semiconductor layer;

a second insulating layer formed on at least a portion of the first insulating layer; and

a conductive structure comprising:

a first portion formed between the first insulating layer and the second insulating layer; and

a second portion formed through the second insulating layer and contiguous to the first portion;

wherein the conductive structure is formed as a substantially homogeneous single seamless unit without a junction between said first portion and said second portion.

2. The semiconductor structure of claim 1 , wherein at least one of the first and second insulating layers comprises silicon dioxide.

3. The semiconductor structure of claim 1 , wherein the conductive structure is formed by a process comprising the steps of:

forming a sacrificial structure on at least a portion of the first insulating layer;

forming the second insulating layer on at least a portion of the sacrificial structure;

forming at least one opening through the second insulating layer to expose at least a portion of the sacrificial structure;

substantially removing the sacrificial structure, thereby leaving a cavity in the second insulating layer; and

filling the cavity and the at least one opening with a conductive material.

4. The semiconductor structure of claim 3 , wherein the step of substantially removing the sacrificial structure comprises etching the sacrificial structure using an isotropic etchant.

5. The semiconductor structure of claim 3 , wherein the step of substantially filling the cavity and the opening with a conductive material comprises depositing the conductive material on sidewalls of the cavity and opening.

6. The semiconductor structure of claim 5 , wherein the conductive material is deposited on the sidewalls of the cavity and opening using a chemical vapor decomposition process.

7. The semiconductor structure of claim 3 , wherein the conductive material comprises tungsten.

8. The semiconductor structure of claim 1 , wherein at least sidewalls of at least the first portion of the conductive structure are defined by removal of a sacrificial structure formed in the semiconductor structure between the first and second insulating layers.

9. The semiconductor structure of claim 1 , wherein the conductive structure comprises a cavity substantially filled with a conductive material, sidewalls of the cavity being defined by removal of a sacrificial structure formed in the semiconductor structure between the first and second insulating layers.

10. The semiconductor structure of claim 1 , wherein a cross-sectional thickness of at least the first portion of the conductive structure is substantially constant throughout.

11. An integrated circuit including at least one semiconductor structure, the at least one semiconductor structure comprising:

a first insulating layer formed on a semiconductor layer;

a second insulating layer formed on at least a portion of the first insulating layer; and

a conductive structure comprising:

a first portion formed between the first insulating layer and the second insulating layer; and

a second portion formed through the second insulating layer and contiguous to the first portion;

wherein the conductive structure is formed as a substantially homogeneous single seamless unit without a junction between said first portion and said second portion.

12. The integrated circuit of claim 11 , wherein the conductive structure is formed by a process comprising the steps of:

forming a sacrificial structure on at least a portion of the first insulating layer;

forming the second insulating layer on at least a portion of the sacrificial structure;

forming at least one opening through the second insulating layer to expose at least a portion of the sacrificial structure;

substantially removing the sacrificial structure, thereby leaving a cavity in the second insulating layer; and

filling the cavity and the at least one opening with a conductive material.

13. The integrated circuit of claim 12 , wherein the step of substantially removing the sacrificial structure comprises etching the sacrificial structure using an isotropic etchant.

14. The integrated circuit of claim 12 , wherein the step of substantially filling the cavity and the opening with a conductive material comprises depositing the conductive material on sidewalls of the cavity and opening.

15. The semiconductor structure of claim 1 , wherein at least the first and second portions of the conductive structure are formed in a same processing step.

16. The semiconductor structure of claim 1 , wherein at least the first and second portions of the conductive structure comprise tungsten.

17. The semiconductor structure of claim 3 , wherein the first portion of the conductive structure is defined by the cavity and the second portion of the conductive structure is defined by the opening.

18. The semiconductor structure of claim 11 , wherein at least the first and second portions of the conductive structure are formed in a same processing step.

19. The semiconductor structure of claim 11 , wherein at least the first and second portions of the conductive structure comprise tungsten.

20. The semiconductor structure of claim 12 , wherein the first portion of the conductive structure is defined by the cavity and the second portion of the conductive structure is defined by the opening.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →