Method to improve writer leakage in SiGe bipolar device
View Patent ↗The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.
1. A semiconductor device, comprising:
a bipolar transistor region, including:
a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration and wherein a thickness of the first SiGe layer is less than 35 nm and has a strain associated therewith;
a second grated SiGe layer located over; and
a silicon capping layer over the second SiGe layer; and
an emitter layer located over the silicon capping layer; and
a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.
2. The device recited in claim 1 , wherein the Ge concentration of the first SiGe layer is about 12% by weight.
3. The device recited in claim 1 , wherein the thickness ranges from about 26 nm to about 34 nm.
4. The device recited in claim 1 , wherein the Ge concentration of the first SiGe ranges from about 5% to about 10% by weight.
5. The device recited in claim 1 , wherein, the second SiGe layer has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.
6. A semiconductor device, comprising:
a bipolar transistor region, including:
a first a silicon/germanium SiGe layer located over a collector tub and having a Ge concentration that ranges from about 5% to about 10% by weight and has a strain associated therewith;
a second grated SiGe layer located over the first SiGe layer; and
a silicon capping layer over the second SiGe layer; and
an emitter layer located over the silicon capping layer; and
a non-bipolar transistor region, including transistors having gate electrodes and source/drains associated therewith.
7. The device recited in claim 6 , wherein a thickness of the first SiGe layer ranges from about 35 nm to about 43 nm.
8. The device recited in claim 6 , wherein the Ge concentration of the first Si/Ge layer is about 7% by weight.
9. The device recited in claim 6 , wherein the thickness of the first Si/Ge layer ranges from about 26 nm to about 34 nm.
10. The device recited in claim 6 , wherein the second SiGe layer has a graded concentration of Ge therein that ranges from about the Ge concentration of the first SiGe at the interface of the first and second SiGe layers to about zero Ge concentration at an upper surface of the second SiGe layer.