Structure and method for improved heat conduction for semiconductor devices
View Patent ↗A thermally conductive structure for a semiconductor integrated circuit and a method for making the structure. The structure comprises one or more vertical and/or horizontal thermally conductive elements disposed proximate a device for improving thermal conductivity from the device to a substrate of the integrated circuit. In one embodiment a heat sink is affixed to the integrated circuit for heat flow from the integrated circuit. The method comprises forming openings in material layers overlying the semiconductor substrate, wherein the openings are disposed proximate the device and extend to the substrate. A thermally conductive material is formed in the openings to provide a thermal path from the device to the substrate.
1. A method for forming a semiconductor integrated circuit, comprising:
forming doped regions in a semiconductor substrate;
forming material layers overlying the substrate;
forming a device in one or more of the material layers;
forming first openings in the material layers, wherein the first openings extend to the substrate and are disposed proximate the device; and
forming thermally conductive material in the first openings.
2. The method of claim 1 further comprising forming second openings in the material layers, wherein the step of forming thermally conductive material in the first openings further comprises forming electrically conductive material in the first and the second openings.
3. The method of claim 2 further comprising forming a first and a second electrical terminal of the device, wherein the thermally conductive material is in physical contact with one of the first or the second electrical terminals, wherein the thermally conductive material does not form a current path.
4. The method of claim 1 further comprising forming electrically conductive layers overlying the material layers, wherein the electrically conductive layers are electrically insulated from the thermally conductive material.
5. The method of claim 4 wherein the thermally conductive material is in thermal communication with the electrically conductive layers.
6. The method of claim 1 wherein the openings comprise a first and a second trench disposed proximate opposing sides of the device.
7. The method of claim 1 wherein the first openings comprise a plurality of substantially vertical openings disposed proximate opposing sides of the device.
8. The method of claim 1 wherein the step of forming the device further comprises forming a resistor.
9. The method of claim 1 wherein the step of forming the first openings comprises etching the openings.
10. The method of claim 1 further comprising forming a thermally conductive top element overlying the device and in thermal communication with the thermally conductive material.
11. The method of claim 10 further comprising forming a thermally conductive element extending between the device and the thermally conductive top element.
12. A method for forming a semiconductor integrated circuit, comprising:
forming doped regions in a semiconductor substrate;
forming a dielectric material region in the substrate;
forming material layers overlying the substrate;
forming a device in one or more of the material layers overlying the dielectric region, wherein the device comprises a first and a second electrical terminal;
forming a current conducting structure in electrical communication with one of the first and the second electrical terminals; and
forming thermally conductive structure proximate the device, wherein the thermally conductive structure comprises a first end in physical contact with the current conducting structure and a second end in thermal communication with the dielectric material region.
13. A method for forming a semiconductor integrated circuit, comprising:
forming doped regions in a semiconductor substrate;
forming a plurality of dielectric material layers overlying and in thermal communication with the substrate;
forming a device in one or more of the plurality of dielectric material layers;
forming openings in the material layers, wherein the openings extend to one of the plurality of dielectric material layers and are disposed proximate the device; and
forming thermally conductive material in the openings.
14. The method of claim 13 wherein certain of the doped regions together with certain of the plurality of dielectric material layers comprise a MOSFET having a gate structure, and wherein the one of the plurality of dielectric layers comprises a hard mask layer overlying the gate structure.
15. The method of claim 13 wherein certain of the doped regions together with certain of the plurality of dielectric material layers comprise a MOSFET having a gate structure, and wherein the one of the plurality of dielectric layers comprises a polysilicon gate of the MOSFET.