I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
View Patent ↗A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
1. An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) pin against positive and negative ESD events, the ESD protection circuit comprising:
a first P-type well formed on a P-conductivity type substrate;
at least one MOS transistor comprising at least one NMOS finger formed on a surface of the substrate within the first P-type well, the at least one NMOS finger including a source connected with VSS, a drain connected with the IC pin, and a gate coupled with VSS;
a second P-type well formed on the substrate, the second P-type well surrounding the first P-type well and being concentric therewith, the second P-type well being connected directly with VSS, the first P-type well being connected to the second P-type well through the substrate;
an N-type well formed on the substrate, the N-type well disposed between the first and second P-type wells and being concentric with the first and second P-type wells, the N-type well being connected with the drain of the at least one NMOS finger;
wherein the second P-type well and the N-type well, together, form a P/N junction diode operative to provide an ESD current path during the negative ESD event.
2. The ESD protection circuit of claim 1 , further comprising a resistor connected between the gate of the at least one NMOS finger and VSS.
3. The ESD protection circuit of claim 2 , wherein the resistor connected between the gate of the at least one NMOS finger and VSS comprises an N-type well resistor.
4. The ESD protection circuit of claim 2 , wherein a resistance of the resistor is greater than about 15 kilohms.
5. The ESD protection circuit of claim 1 , wherein the first P-type well has a first resistance associated therewith and the second P-type well has a second resistance associated therewith, a resistance of the substrate connecting the first and second P-type wells being substantially greater than the first resistance or second resistance.
6. The ESD protection circuit of claim 1 , wherein the at least one MOS transistor comprises a plurality of NMOS fingers, each of at least a subset of the plurality of NMOS fingers being disposed laterally adjacent to one another and including a source connected with VSS, a drain connected with the IC pin, and a gate coupled with VSS.
7. The ESD protection circuit of claim 1 , wherein the IC pin to be protected against positive and negative ESD events comprises one of a power pin and an input/output (I/O) pin.
8. The ESD protection circuit of claim 1 , further comprising:
a first shallow trench isolation (STI) formed on the surface of the substrate between the first P-type well and the N-type well; and
a second STI formed on the surface of the substrate between the N-type well and the second P-type well.
9. The ESD protection circuit of claim 8 , wherein a depth of the N-type well in the substrate is greater than a depth of each of the first and second STIs.
10. The ESD protection circuit of claim 1 , further comprising:
at least a first P-type diffusion ring formed on the surface of the substrate between the first P-type well and the N-type well, the first P-type diffusion ring being concentric with the first P-type well; and
a PMOSFET having a source connected with the P-type diffusion ring, a drain connected with the IC pin, and a gate connected with VDD.
11. The ESD protection circuit of claim 10 , wherein the PMOSFET is turned on during the positive ESD event and is operative to inject current from the IC pin into the first P-type well through the first P-type diffusion ring.
12. The ESD protection circuit of claim 10 , wherein first P-type diffusion ring is connected with VSS through the substrate.
13. The ESD protection circuit of claim 10 , wherein the first P-type diffusion ring is formed within the first P-type well and is operative as a trigger node of the at least one NMOS finger, whereby a trigger voltage of the at least one NMOS finger is lowered.
14. The ESD protection circuit of claim 10 , further comprising a second P-type diffusion ring formed on the surface of the substrate between the N-type well and the second P-type well, the second P-type diffusion ring being concentric with the first P-type well and connected directly with VSS, the first P-type diffusion ring being connected to the second P-type diffusion ring through the substrate.
15. The ESD protection circuit of claim 14 , wherein the second P-type diffusion ring is formed within the second P-type well surrounding the N-type well, the second P-type diffusion ring providing an electrical connection between the second P-type well and VSS.
16. The ESD protection circuit of claim 14 , further comprising:
a first shallow trench isolation (STI) formed on the surface of the substrate between the first P-type well and the first P-type diffusion ring;
a second STI formed on the surface of the substrate between the first P-type diffusion ring and the N-type well; and
a third STI formed on the surface of the substrate between the N-type well and the second P-type diffusion ring.
17. The ESD protection circuit of claim 16 , wherein a depth of the N-type well in the substrate is greater than a depth of each of the first, second and third STIs.
18. The ESD protection circuit of claim 1 , wherein the N-type well is connected directed with the IC pin and is operative to suppress a substrate current flowing to VSS through the second P-type well to thereby lower a trigger voltage of the at least one MOS transistor during the positive ESD event.
19. An integrated circuit (IC) comprising at least one electrostatic discharge (ESD) protection circuit for protecting a pin of the IC against positive and negative ESD events, the at least one ESD protection circuit comprising:
a first P-type well formed on a P-conductivity type substrate;
at least one MOS transistor comprising at least one NMOS finger formed on a surface of the substrate within the first P-type well, the at least one NMOS finger including a source connected with VSS, a drain connected with the IC pin, and a gate coupled with VSS;
a second P-type well formed on the substrate, the second P-type well surrounding the first P-type well and being concentric therewith, the second P-type well being connected directly with VSS, the first P-type well being connected to the second P-type well through the substrate;
an N-type well formed on the substrate, the N-type well disposed between the first and second P-type wells and being concentric with the first and second P-type wells, the N-type well being connected with the drain of the at least one NMOS finger;
wherein the second P-type well and the N-type well, together, form a P/N junction diode operative to provide an ESD current path during the negative ESD event.
20. An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) pin against positive and negative ESD events, the ESD protection circuit comprising:
a first well of a first conductivity type formed on a semiconductor substrate;
at least one transistor comprising at least one MOS finger formed on a surface of the substrate within the first well, the at least one MOS finger including a source connected with a first voltage supply, a drain connected with the IC pin, and a gate coupled with the first voltage supply;
a second well of the first conductivity type formed on the substrate, the second well surrounding the first well and being concentric therewith, the second well being connected directly with the first voltage supply, the first well being connected to the second well through the substrate;
a third well of a second conductivity type formed on the substrate, the second conductivity type being opposite in polarity to the first conductivity type, the third well disposed between the first and second wells and being concentric with the first and second wells, the third well being connected with the drain of the at least one MOS finger;
wherein the second well and the third well, together, form a P/N junction diode operative to provide an ESD current path during the negative ESD event.