IP Library › Assignment 059723/0382
Patent Assignment
Reel/Frame 059723/0382

RELEASE OF SECURITY INTEREST

Recorded: 2022-04-15 Received: 2022-04-15 Pages: 236
Assignor
Assignees
HILCO PATENT ACQUISITION 56, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
BELL SEMICONDUCTOR, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
BELL NORTHERN RESEARCH, LLC
401 N. MICHIGAN AVE., SUITE 1630, CHICAGO, IL, 60611, UNITED STATES
Covered Applications (100)
STACKED INTERCONNECT HEAT SINK
App. No. 14/678,223
→
COORDINATIVE DATACENTER PROCESSING IN A NETWORK-BASED COMMUNICATION SYSTEM
App. No. 14/531,775
→
MANAGING DATA STREAMS FOR A COMMUNICATION NETWORK
App. No. 14/335,249
→
RELIABILITY OF A CONNECTION DURING A COMMUNICATION SESSION ON A NETWORK DEVICE
App. No. 14/335,171
→
CUSTOMIZING NETWORK-LEVEL SETTINGS FOR A NETWORK DEVICE ON A COMMUNICATION NETWORK
App. No. 14/335,215
→
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
App. No. 14/251,258
→
CONTACT SUPPORT PILLAR STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
App. No. 13/934,110
→
STACKED INTERCONNECT HEAT SINK
App. No. 13/921,707
→
METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
App. No. 13/775,922
→
SOLDER INTERCONNECT BY ADDITION OF COPPER
App. No. 13/752,524
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METHOD OF MANUFACTURING AN ELECTRONIC DEVICE PACKAGE
App. No. 13/677,547
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ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER
App. No. 13/656,092
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SOLDERING METHOD AND RELATED DEVICE FOR IMPROVED RESISTANCE TO BRITTLE FRACTURE
App. No. 13/552,266
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ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY
App. No. 13/344,207
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METHODS FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
App. No. 13/252,632
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LOW-COST 3D FACE-TO-FACE OUT ASSEMBLY
App. No. 13/217,857
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ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
App. No. 13/174,970
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 13/110,581
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SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
App. No. 13/093,032
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CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
App. No. 13/041,674
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DECOUPLING CAPACITOR
App. No. 13/032,429
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MITIGATION OF WHISKERS IN SN-FILMS
App. No. 13/059,502
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METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS
App. No. 12/969,836
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INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
App. No. 12/969,852
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Low Cost 3D-Face to Face Fan Out F2FFO Assembly
App. No. 61/377,171
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STACKED INTERCONNECT HEAT SINK
App. No. 12/840,016
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BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE
App. No. 12/678,405
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METHOD AND ARTICLE OF MANUFACTURE FOR WIRE BONDING WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS
App. No. 12/692,209
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INTEGRATED HEAT SINK
App. No. 12/689,806
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SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
App. No. 12/625,457
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CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
App. No. 12/546,083
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WHISKER-FREE LEAD FRAMES
App. No. 12/462,069
→
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 12/506,746
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SOLDER INTERCONNECT BY ADDITION OF COPPER
App. No. 12/501,686
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LEAD FRAME DESIGN TO IMPROVE RELIABILITY
App. No. 12/486,592
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METHOD OF GENERATING A LEADFRAME IC PACKAGE MODEL, A LEADFRAME MODELER AND AN IC DESIGN SYSTEM
App. No. 12/485,238
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ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
App. No. 12/483,139
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ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY
App. No. 12/471,982
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SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION
App. No. 12/469,985
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CIRCUIT APPARATUS INCLUDING REMOVABLE BOND PAD EXTENSION
App. No. 12/463,718
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SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT
App. No. 12/432,763
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SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
App. No. 12/337,519
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WIRE BONDING OVER ACTIVE CIRCUITS
App. No. 12/331,561
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PREFERENTIALLY COOLED ELECTRONIC DEVICE
App. No. 12/327,987
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ELECTRICAL DEVICES HAVING ADJUSTABLE CAPACITANCE
App. No. 12/253,403
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INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
App. No. 12/283,820
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PACKAGE WITH POWER AND GROUND THROUGH VIA
App. No. 12/206,786
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THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS
App. No. 12/194,706
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PLASTIC OVERMOLDED PACKAGES WITH MECHANCIALLY DECOUPLED LID ATTACH ATTACHMENT
App. No. 12/228,720
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MANUFACTURE OF DEVICES INCLUDING SOLDER BUMPS
App. No. 12/220,182
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METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
App. No. 12/171,903
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HIGH THERMAL PERFORMANCE PACKAGING FOR CIRCUIT DIES
App. No. 12/160,233
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CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES
App. No. 12/163,453
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ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
App. No. 12/139,185
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STRUCTURE AND METHOD FOR FABRICATING FLIP CHIP DEVICES
App. No. 11/884,328
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METHOD OF MAKING ELECTRONIC ENTITIES
App. No. 12/154,794
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SOLUTION FOR PACKAGE CROSSTALK MINIMIZATION
App. No. 61/055,505
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FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES
App. No. 12/121,363
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PAD CURRENT SPLITTING
App. No. 12/119,575
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ELECTRONIC PACKAGES
App. No. 12/151,108
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HEAT DISSIPATION FOR INTEGRATED CIRCUIT
App. No. 12/061,728
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INTEGRATED CIRCUIT PACKAGE FOR HIGH-SPEED SIGNALS
App. No. 12/060,387
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LEADFRAME DESIGNS FOR PLASTIC OVERMOLD PACKAGES
App. No. 12/079,124
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PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE USING SOLDER AND FILM ADHESIVE
App. No. 12/038,911
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BALL GRID ARRAY PACKAGE LAYOUT SUPPORTING MANY VOLTAGE SPLITS AND FLEXIBLE SPLIT LOCATIONS
App. No. 12/034,745
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INTEGRATED CIRCUIT PACKAGE INCLUDING WIRE BONDS
App. No. 11/973,859
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INTEGRATED CIRCUIT DEVICE INCORPORATING METALLURGICAL BOND TO ENHANCE THERMAL CONDUCTION TO A HEAT SINK
App. No. 11/868,624
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INTEGRATED CIRCUIT PACKAGE WITH SPUTTERED HEAT SINK FOR IMPROVED THERMAL PERFORMANCE
App. No. 11/772,267
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SEMICONDUCTOR DEVICE PACKAGE WITH BASE FEATURES TO REDUCE LEAKAGE
App. No. 11/788,346
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SYSTEMS AND METHODS FOR SUPPORTING A SUBSET OF MULTIPLE INTERFACE TYPES IN A SEMICONDUCTOR DEVICE
App. No. 11/684,674
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WIRE BONDING METHOD AND RELATED DEVICE FOR HIGH-FREQUENCY APPLICATIONS
App. No. 11/717,227
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FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
App. No. 11/670,031
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ELECTRONIC COMPONENT CONNECTION SUPPORT STRUCTURES INCLUDING AIR AS A DIELECTRIC
App. No. 11/641,989
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WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
App. No. 11/565,701
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SYSTEMS AND METHODS FOR DISTRIBUTING I/O IN A SEMICONDUCTOR DEVICE
App. No. 11/530,550
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ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER
App. No. 11/469,960
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HEAT DISSIPATION IN INTEGRATED CIRCUITS
App. No. 11/468,901
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INTEGRATED CIRCUIT PACKAGE AND SYSTEM INTERFACE
App. No. 11/506,680
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PLASTIC OVERMOLDED PACKAGES WITH MECHANICALLY DECOUPLED LID ATTACH ATTACHMENT
App. No. 11/505,152
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ON-CHIP SENSOR ARRAY FOR TEMPERATURE MANAGEMENT IN INTEGRATED CIRCUITS
App. No. 11/460,459
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INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
App. No. 11/494,221
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SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFORE
App. No. 11/459,249
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REINFORCED BOND PAD FOR A SEMICONDUCTOR DEVICE
App. No. 11/448,560
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SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMODATE HIGH SPEED CIRCUITRY GROUND ISOLATION
App. No. 11/399,723
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METHODS AND APPARATUS FOR INTEGRATED CIRCUIT BALL BONDING WITH SUBSTANTIALLY PERPENDICULAR WIRE BOND PROFILES
App. No. 11/395,779
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DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
App. No. 11/277,188
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METHODS AND APPARATUS FOR WIRE BONDING WITH WIRE LENGTH ADJUSTMENT IN AN INTEGRATED CIRCUIT
App. No. 11/385,245
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METHODS AND APPARATUS FOR DETERMINING PAD HEIGHT FOR A WIRE-BONDING OPERATION IN AN INTEGRATED CIRCUIT
App. No. 11/385,086
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LOW THERMAL RESISTANCE ASSEMBLY FOR FLIP CHIP APPLICATIONS
App. No. 11/375,302
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FLEXIBLE CIRCUIT SUBSTRATE FOR FLIP-CHIP-ON-FLEX APPLICATIONS
App. No. 11/360,200
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POWER CONFIGURATION METHOD FOR STRUCTURED ASICS
App. No. 11/334,870
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SOCKETLESS/BOARDLESS TEST INTERPOSER CARD
App. No. 11/324,119
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METHOD OF USING AUTOMATED TEST EQUIPMENT TO SCREEN FOR LEAKAGE INDUCING DEFECTS AFTER CALIBRATION TO INTRINSIC LEAKAGE
App. No. 11/300,789
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SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE
App. No. 11/304,862
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INTEGRATED CIRCUIT DEVICE HAVING FLEXIBLE LEADFRAME
App. No. 11/302,690
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INTEGRATED CIRCUIT HAVING BOND PAD WITH IMPROVED THERMAL AND MECHANICAL PROPERTIES
App. No. 11/298,030
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SCALING OF FUNCTIONAL ASSIGNMENTS IN PACKAGES
App. No. 11/283,340
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ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
App. No. 11/260,334
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I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
App. No. 11/258,253
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INTEGRATED CIRCUIT DEVICE INCORPORATING METALLURIGICAL BOND TO ENHANCE THERMAL CONDUCTION TO A HEAT SINK
App. No. 11/235,920
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