IP Library Granted Patent US 8,125,091
Granted Patent B2
US 8,125,091 · App. 12/331,561 · Granted Feb 28, 2012

Wire bonding over active circuits

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Quick Facts
Patent No.
US 8,125,091
App. No.
12/331,561
Granted
Feb 28, 2012
Kind
B2
Abstract

A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.

Claims (52)

1. A semiconductor device, comprising:

a semiconductor die mounted over a package substrate and having a bond pad located thereover;

a stud bump located on said bond pad, said stud bump consisting substantially of a first metal;

a first wire bonded to said stud bump, said first wire consisting substantially of a different second metal; and

a second wire bonded directly to a second bond pad located over said die.

2. The semiconductor device as recited in claim 1 , wherein said second metal is harder than said first metal.

3. The semiconductor device as recited in claim 1 , wherein said first metal is more malleable than said second metal.

4. The semiconductor device as recited in claim 1 , wherein said stud bump comprises gold.

5. The semiconductor device as recited in claim 1 , wherein said first wire comprises copper.

6. The semiconductor device as recited in claim 4 , wherein said stud bump further comprises palladium.

7. The semiconductor device as recited in claim 1 , further comprising a low-k dielectric layer or an active circuit under said bond pad.

8. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor die over a package substrate, said die having a bond pad formed thereover;

forming a stud bump on said bond pad, said stud bump consisting substantially of a first metal;

bonding a first end of a bond wire to said stud bump, said wire consisting substantially of a different second metal;

bonding a second end of said bond wire to a bond site on said package substrate; and

doping said stud bump or said wire with a dopant selected to inhibit intermetallic formation between said stud bump and said wire.

9. The method as recited in claim 8 , wherein said first metal has a lower modulus than said second metal.

10. The method as recited in claim 8 , wherein said first metal is more malleable than said second metal.

11. The method as recited in claim 8 , wherein said stud bump is formed by a ball bonding process.

12. The method as recited in claim 8 , wherein said semiconductor die comprises a low-k dielectric under said bond pad.

13. The method as recited in claim 8 , wherein said stud bump comprises gold and said wire comprises copper.

14. A semiconductor device, comprising:

an integrated circuit package having a substrate;

a semiconductor die having first and second bond pads formed thereover and mounted over said substrate;

a gold stud bump bonded to said first bond pad;

a copper first wire connecting said gold stud bump and a bond site on said substrate; and

a second wire connected directly to said second bond pad.

15. The semiconductor device recited in claim 14 , wherein said gold stud bump is formed by a ball bonding process.

16. The semiconductor device recited in claim 14 , wherein said gold stud bump comprises palladium.

17. A semiconductor device, comprising:

a semiconductor die mounted over a package substrate and having a bond pad located thereover;

a stud bump located on said bond pad, said stud bump consisting substantially of a first metal;

a wire bonded to said stud bump, said wire consisting substantially of a different second metal; and

a low-k dielectric layer located between said bond pad and said semiconductor die.

18. A semiconductor device, comprising:

a semiconductor die mounted over a package substrate and having a bond pad located thereover;

a stud bump located on said bond pad, said stud bump consisting substantially of a first metal;

a wire bonded to said stud bump, said wire consisting substantially of a different second metal; and

an active circuit located between said bond pad and said semiconductor die.

19. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor die over a package substrate, said die having a bond pad formed thereover;

forming a stud bump on said bond pad, said stud bump consisting substantially of a first metal;

forming a low-k dielectric layer between said bond pad and said semiconductor die;

bonding a first end of a bond wire to said stud bump, said bond wire consisting substantially of a different second metal; and

bonding a second end of said bond wire to a bond site on said package substrate.

20. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor die over a package substrate, said die having a bond pad formed thereover;

forming a stud bump on said bond pad, said stud bump consisting substantially of a first metal;

forming an active circuit between said bond pad and said semiconductor die;

bonding a first end of a bond wire to said stud bump, said bond wire consisting substantially of a different second metal; and

bonding a second end of said bond wire to a bond site on said package substrate.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: LOW, QWAI H.
To: LSI CORPORATION
Reel/Frame 021954/0800 →