Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
View Patent ↗The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.
1. A semiconductor device, comprising:
an interconnect layer located over a semiconductor substrate;
a first passivation layer located over the interconnect layer and having a solder bump support opening formed therein;
a second passivation layer located over the first passivation layer and extending along the sidewall of the first passivation layer within the opening;
support pillars located within the solder bump support opening and on the interconnect layer, the support pillars comprising a conductive material, wherein the second passivation layer is located between the sidewall of the first passivation layer and at least one of the support pillars; and
an under bump metallization (UBM) layer located over and between the support pillars, and wherein the UBM layer extends over and contacts the second passivation layer.
2. The semiconductor device recited in claim 1 , wherein the support pillars include a barrier layer that is located on the interconnect layer and on the support pillars.
3. The semiconductor device recited in claim 1 , wherein the support pillars form a first group of support pillars and further including a second group of support pillars located within the solder bump support opening and between ones of the first group of support pillars and comprising a different conductive material from the first group.
4. The semiconductor device recited in claim 3 , wherein the conductive material comprises copper and the different conductive material comprises aluminum.
5. The semiconductor device recited in claim 4 , wherein the UBM layer is located on the aluminum.
6. The semiconductor device recited in claim 1 , further comprising:
a plurality of groups of the support pillars with each group having a UBM layer located thereover; and
a solder bump located on each of the UBM layers and wherein the semiconductor device comprises an integrated circuit (IC) flip chip.
7. The semiconductor device recited in claim 6 , wherein the solder bump is comprised of a lead solder or a lead-free solder.
8. A semiconductor device, comprising:
an interconnect layer located over a semiconductor substrate;
a passivation layer located over the interconnect layer and having a solder bump support opening formed therein;
support pillars located within the solder bump support opening, the support pillars comprising a conductive material; and
an under bump metallization (UBM) layer located over the support pillars, wherein the UBM layer is located between at least one of the support pillars and a sidewall of the opening formed in the passivation layer and contacts the sidewall of the opening.
9. The semiconductor device recited in claim 8 wherein a portion of the UBM layer is located within the opening and between sidewalls of the passivation layer that define the opening and at least one of the support.
10. The semiconductor device recited in claim 8 , wherein the support pillars include a barrier layer that is located on the interconnect layer and on the support pillars.