Bond pad support structure for semiconductor device
View Patent ↗According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure.
1. An integrated circuit (IC) comprising:
a bond pad;
a first passivation structure directly underneath and in direct contact with a first portion of the bond pad; and
a first metallization layer under the bond pad and the first passivation structure, wherein the first metallization layer comprises a first metal structure directly underneath and in direct contact with both (i) a second portion of the bond pad and (ii) the first passivation structure;
a second metallization layer under the first metallization layer; and
dielectric material between the first and second metallization layers, wherein a portion of the second metallization layer directly underneath the bond pad comprises two or more metal structures corresponding to two or more distinct routing paths.
2. The invention of claim 1 , wherein the first metallization layer comprises one or more distinct routing paths not below the bond pad and not directly connected to the first metal structure.
3. The invention of claim 1 , wherein the first metallization layer does not have more than one distinct routing path under the bond pad.
4. The invention of claim 1 , wherein the dielectric material is low-k dielectric material.
5. The invention of claim 4 , wherein the low-k dielectric materials have a dielectric constant k of less than 3.
6. The invention of claim 4 , wherein the low-k dielectric materials have a Young's modulus of less than 40 GPa.
7. The invention of claim 1 , wherein there are no metal vias between the first and second metallization layers in the volume underneath the bond pad.
8. The invention of claim 1 , wherein the bond pad is part of a larger structure that also includes a probe region directly connected to the bond pad.
9. The IC of claim 1 , wherein the first passivation structure helps prevent permanent damage to the IC during wire-bonding to the bond pad.
10. The invention of claim 1 , wherein the first metal structure is a substantially continuous planar metal structure having substantially the same area as the bond pad, located underneath and directly connected to the bond pad.
11. The invention of claim 1 , further comprising a second passivation structure above the first metallization layer.
12. The invention of claim 11 , wherein the second passivation structure is separated from the first passivation structure by the second portion of the bond pad that is in direct contact with the first metallization layer.
13. The invention of claim 12 , wherein the first passivation structure is substantially in the shape of a square substantially centered in an opening in the second passivation structure.
14. The invention of claim 12 , wherein the first passivation structure is substantially in the shape of an ellipse substantially centered in an opening in the second passivation structure.
15. The invention of claim 11 , wherein the first passivation structure and the second passivation structure are made of substantially identical passivation material.
16. An integrated circuit (IC) comprising:
a bond pad;
a first metallization layer under and in direct contact with the bond pad;
a second metallization layer under the first metallization layer;
low-k dielectric material between the first and second metallization layers, wherein: a portion of the second metallization layer under the bond pad comprises two or more metal lines that are (i) part of two more distinct routing paths in the IC and (ii) separated by low-k dielectric material;
at least one of the metal lines in the portion of the second metallization layer under the bond pad is directly connected to the first metallization layer by one or more metal features in the low-k dielectric material; and
at least one of the metal lines in the portion of the second metallization layer under the bond pad is not directly connected to the first metallization layer by any metal feature in the first low-k dielectric material.
17. The invention of claim 16 , wherein fill density of metal features in the low-k dielectric material between the first and second metallization layers in the volume underneath the bond pad is at least 30%.
18. The invention of claim 17 , wherein the fill density of metal features in the low-k dielectric material between the first and second metallization layers in the volume underneath the bond pad is 60-80%.
19. The invention of claim 16 , wherein the one or more metal features helps prevent permanent damage to the IC during wire-bonding to the bond pad.
20. The invention of claim 1 , wherein the first passivation structure is located substantially at the center of the bond pad.