IP Library Granted Patent US 8,288,269
Granted Patent B2
US 8,288,269 · App. 13/252,632 · Granted Oct 16, 2012

Methods for avoiding parasitic capacitance in an integrated circuit package

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,288,269
App. No.
13/252,632
Granted
Oct 16, 2012
Kind
B2
Abstract

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Claims (41)

1. A method, comprising steps of:

forming a first electrically conductive layer including a plurality of rows of contact pads;

forming an electrically insulating layer on the first electrically conductive layer; and

forming a second electrically conductive layer over the electrically insulating layer such that there is no intermediate conductive layer between the first and second electrically conductive layers, the second electrically conductive layer comprising metal and a plurality of cutouts wherein each cutout encloses an electrically insulating area within the second electrically conductive layer and wherein each electrically insulating area completely overlaps a corresponding one of the contact pads such that there is substantially no overlap of the rows of contact pads with metal in the second electrically conductive layer.

2. The method of claim 1 , further comprising:

forming the contact pads as transmit and receive rows of contact pads;

forming the second electrically conductive layer as a routing layer including routing traces such that the contact pads are operable with the second electrically conductive layer for converting a serial data stream to or from a parallel data stream; and

forming the cutouts in rows corresponding to and aligned with the rows of contact pads.

3. The method of claim 1 , wherein the cutouts have the same dimensions as the contact pads.

4. The method of claim 1 , further comprising:

forming a third electrically conductive layer comprising metal and a plurality of cutouts above the second electrically conductive layer; and

forming a second electrically insulating layer between the second and third electrically conductive layers, each of the cutouts in the third electrically conductive layer enclosing an electrically insulating area within the third electrically conductive layer such that there is substantially no overlap of the rows of contact pads with metal in the third electrically conductive layer.

5. The method of claim 4 , further comprising:

forming the third electrically conductive layer as a ground return metal layer; and

forming the second electrically conductive layer as a routing metal layer electrically connected to the first electrically conductive layer.

6. The method of claim 1 , further comprising:

forming the second electrically conductive layer as a routing layer including routing traces; and

forming the cutouts in rows corresponding to and aligned with the rows of contact pads.

7. The method of claim 1 , further comprising:

forming a third electrically conductive layer comprising metal and including rows of cutouts, each of the cutouts in the third electrically conductive layer enclosing an electrically insulating layer in the third electrically conductive layer; and

forming a second electrically insulating layer between the second and third electrically conductive layers, wherein the rows of cutouts in the third electrically conductive layer correspond to and are aligned with the rows of contact pads such that there is substantially no overlap of the rows of contact pads with metal in the third electrically conductive layer and there is no intermediate conductive layer between the third electrically conductive layer and the first electrically conductive layer other than the second electrically conductive layer.

8. The method of claim 7 , wherein the second electrically conductive layer is a routing metal layer and the third electrically conductive layer is a ground plane layer.

9. The method of claim 1 , further including electrically connecting the first electrically conductive layer to a printed circuit board.

10. A method, comprising steps of:

forming a first layer including a plurality of rows of electrical contacts;

forming a plurality of electrically conductive layers immediately proximate the first electrically conductive layer, each of the electrically conductive layers including a plurality of electrically insulating areas such that there is substantially no overlap of the rows of contact pads with metal in the plurality of electrically conductive layers; and

forming a plurality of dielectric layers separating, respectively, the electrically conductive layers and the first layer from each other.

11. The method of claim 10 , further comprising forming a plurality of rows of cutouts in each of the electrically conductive layers corresponding to and aligned with the rows of electrical contacts, each of the cutouts enclosing one of the electrically insulating areas.

12. The method of claim 11 , wherein one of the electrically conductive layers is a routing metal layer including routing traces.

13. The method of claim 11 , further comprising forming the cutouts to completely overlap corresponding electrical contacts.

14. The method of claim 11 , further comprising:

forming the electrical contacts as transmit and receive rows of contact pads; and

forming vias connecting the contact pads with one of the electrically conductive layers.

15. The method of claim 14 , further comprising forming one of the electrically conductive layers as a routing layer comprising routing traces and another of the electrically conductive layers as a ground return metal layer.

16. The method of claim 15 , further comprising electrically connecting the contact pads to a printed circuit board.

17. The method of claim 11 , further comprising electrically connecting the electrical contacts to a printed circuit board.

18. The method of claim 17 , further comprising forming the cutouts to completely overlap corresponding electrical contacts.

19. The method of claim 18 , further comprising:

forming the electrical contacts in transmit and receive rows; and

forming vias connecting the electrical contacts with one of the electrically conductive layers.

20. The method of claim 11 , further comprising forming the cutouts to completely overlap corresponding electrical contacts.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (2)
Division 11277188 · Mar 22, 2006
Related Publication 20120021599A1 · Jan 26, 2012