Decoupling capacitor
View Patent ↗An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.
1. An electronic device package, comprising:
a first electrode of a package substrate, said first electrode configured to operate at a first DC potential and having fingers formed from a first metal level located over a dielectric material layer of the package substrate;
a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via passing through said dielectric material layer to conductively connect said second electrode to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes.
2. The electronic device package as recited in claim 1 , wherein said first DC potential is ground.
3. The electronic device package as recited in 1 , wherein said interdigitated electrodes have an aspect ratio of at least about 1:1.
4. The electronic device package as recited in claim 1 , wherein a capacitance between said first and second electrodes is in a range from about 10 fF/μm 2 to about 100 fF/μm 2 .
5. The electronic device package as recited in claim 1 , wherein said first electrode is connected to a third metal level configured to provide said first DC potential.
6. An electronic device package, comprising:
a first electrode of a package substrate configured to operate at a first DC potential and having fingers formed from a first metal level;
a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via that conductively connects said second electrode to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, and, further comprising an integrated circuit die attached to said package substrate, said die being configured to receive power and ground from said first and second metal levels.
7. An electronic device package, comprising:
a first electrode of a package substrate configured to operate at a first DC potential and having fingers formed from a first metal level;
a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via that conductively connects said second electrode to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, wherein said first metal level is located on a first dielectric material having a first dielectric constant, and a second dielectric layer having a second different dielectric constant is located between said first and second metal levels.
8. An electronic device package, comprising:
a first electrode of a package substrate configured to operate at a first DC potential and having fingers formed from a first metal level;
a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via that conductively connects said second electrode to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, wherein said first and second electrodes may be circumscribed by a polygon having a maximum side length no greater than about three times a diameter of said via.
9. An electronic device package, comprising:
a first electrode of a package substrate configured to operate at a first DC potential and having fingers formed from a first metal level;
a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via that conductively connects said second electrode to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, and, further comprising a printed circuit board electrically connected to said package substrate by way of solder balls, said printed circuit board being configured to provide power to one of said first and second electrodes and ground to the other of said first and second electrodes though said solder balls.
10. A method of decoupling power on an electronic device package, comprising:
forming a first electrode of a package substrate, said first electrode having fingers formed from a first metal level located over a dielectric material layer of the package substrate, and configuring said first electrode to operate at a first DC potential;
forming a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
connecting said second electrode with a via formed through said dielectric material layer to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes.
11. The method as recited in claim 10 , wherein said first DC potential is ground.
12. The method as recited in claim 10 , wherein said interdigitated electrodes have an aspect ratio of at least about 1:1.
13. The method as recited in claim 10 , wherein a capacitance between said first and second electrodes is in a range from about 10 fF/μm 2 to about 100 fF/μm 2 .
14. The method as recited in claim 10 , further comprising connecting said first electrode to a third metal level configured to provide said first DC potential.
15. A method of decoupling power on an electronic device package, comprising:
forming a first electrode of a package substrate, said first electrode having fingers formed from a first metal level, and configuring said first electrode to operate at a first DC potential;
forming a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
connecting said second electrode with a via to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, and, further comprising configuring an integrated circuit die to receive power and ground from said first and second metal levels.
16. A method of decoupling power on an electronic device package, comprising:.
forming a first electrode of a package substrate, said first electrode having fingers formed from a first metal level, and configuring said first electrode to operate at a first DC potential;
forming a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
connecting said second electrode with a via to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, wherein said first metal level is located on a first dielectric material having a first dielectric constant, and a second dielectric layer having a second different dielectric constant is located between said first and second metal levels.
17. A method of decoupling power on an electronic device package, comprising:
forming a first electrode of a package substrate, said first electrode having fingers formed from a first metal level, and configuring said first electrode to operate at a first DC potential;
forming a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
connecting said second electrode with a via to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, wherein said first and second electrodes may be circumscribed by a polygon having a maximum side length no greater than about three times a diameter of said via.
18. A method of decoupling power on an electronic device package, comprising:
forming a first electrode of a package substrate, said first electrode having fingers formed from a first metal level, and configuring said first electrode to operate at a first DC potential;
forming a second electrode of said package substrate having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
connecting said second electrode with a via to a second metal level configured to operate at a second DC potential, thereby capacitively coupling said first and second DC potentials through said interdigitated electrodes, further comprising conductively coupling said package substrate to a printed circuit board by way of solder balls, said printed circuit board being configured to provide power to one of said first and second electrodes and ground to the other of said first and second electrodes through said solder balls.
19. A library of standard elements for use in an electronic device package substrate, comprising:
a standard element corresponding to a decoupling capacitor, including:
a first electrode configured to operate at a first DC potential and having fingers formed from a first metal level located over a dielectric material layer of the electronic package substrate;
a second electrode having fingers formed from said first metal level, fingers of said first and second electrodes being interdigitated; and
a via passing through said dielectric material layer to conductively connect that conductively connects said second electrode to a second metal level configured to operate at a second DC potential.
20. The library as recited in claim 19 , wherein said standard element further includes a second via that connects said first electrode to a third metal level configured to provide said first DC potential.