IP Library Granted Patent US 7,430,700
Granted Patent B2
US 7,430,700 · App. 11/670,031 · Granted Sep 30, 2008

Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)

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Quick Facts
Patent No.
US 7,430,700
App. No.
11/670,031
Granted
Sep 30, 2008
Kind
B2
Abstract

The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

Claims (18)

1. A method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow, said method comprising the steps of:

a) pausing on one of said patterns in said test flow;

b) providing an appropriate computer program;

c) having said appropriate computer program query a user regarding a plurality of items;

d) having said appropriate computer program start processing one inspect vector within an inspect vector range by characterizing each signal on said inspect vector with non-strobed characters to determine whether an output signal is being driven;

e) if said output signal is being driven, having said appropriate computer program change said non-strobed character to a high or low strobe character to provide a new vector, depending on whether said output signal is an output that is being driven to a high or low state;

f) running said pattern with said new vector for consecutive passes required at both minimum and maximum VDD device power settings to insure said new vector is not marginal;

g) if any of said high or low strobe characters fail during consecutive passes at said minimum and maximum VDD device power settings, resetting said high or low strobe characters back to said non-strobed characters and retesting; and

h) repeating steps (d) through (g) as necessary.

2. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding a start vector address in step (c).

3. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding the first inspect vector address in step (c).

4. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding the last inspect vector address in step (c).

5. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding consecutive passes for new vectors in step (c).

6. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding data logging requirements in step (c).

7. A method as defined in claim 1 , wherein said appropriate computer program queries the user regarding file name for output storage in step (c).

8. A method as defined in claim 1 , wherein said inspect vector range is defined between a first inspect vector address and a last inspect vector address.

9. A method as defined in claim 8 , wherein said appropriate computer program queries the user regarding said first inspect vector address and said last inspect vector address in step (c).

10. A method as defined in claim 1 , wherein said non-strobed characters do not add to said fault coverage of said test flow.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →