IP Library Granted Patent US 8,084,857
Granted Patent B2
US 8,084,857 · App. 12/692,209 · Granted Dec 27, 2011

Method and article of manufacture for wire bonding with staggered differential wire bond pairs

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Quick Facts
Patent No.
US 8,084,857
App. No.
12/692,209
Granted
Dec 27, 2011
Kind
B2
Abstract

A method and article of manufacture for performing wire-bonding operations in an integrated circuit. In one aspect, the operations include the steps of bonding a wire to a first bond site in the integrated circuit and terminating the wire at a second bond site. The bonding and terminating steps are repeated for at least two differential wire bond pairs, and proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles.

Claims (28)

1. A method for performing a wire-bonding operation in an integrated circuit, utilizing a bonding tool, the method comprising the steps of:

bonding a wire to a first bond site in the integrated circuit; and

terminating the wire at a second bond site;

wherein the bonding and terminating steps are repeated for at least two differential wire bond pairs, wherein individual wires within each of the at least two differential wire bond pairs have substantially similar wire bond profiles, and wherein proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles. and

wherein individual wires within each of the at least two differential wire bond pairs are adjacent to each other without other wires therebetween in a plan view of the integrated circuit.

2. The method of claim 1 , wherein the step of bonding a wire to a first bond site comprises the step of bonding a wire to a die of the integrated circuit.

3. The method of claim 1 , wherein the step of terminating a wire at a second bond site comprises the step of terminating a wire at an integrated circuit package substrate.

4. The method of claim 3 , wherein the step of terminating the wire at an integrated circuit package substrate comprises the step of terminating the wire at a substrate on which one or more circuit elements are disposed, and to which the at least two differential wire bond pairs are terminated.

5. The method of claim 1 , wherein a first differential wire bond pair of the at least two differential wire bond pairs comprises data signal input wire bonds, and a second differential wire bond pair of the at least two differential wire bond pairs comprises data signal output wire bonds.

6. The method of claim 1 , wherein the proximate differential wire bond pairs have wire bond profiles with different heights above the first bond site in the integrated circuit.

7. The method of claim 1 , wherein the proximate differential wire bond pairs have wire bond profiles with different lengths from the first bond site in the integrated circuit.

8. The method of claim 1 , wherein the at least two differential wire bond pairs are staggered in length from the first bond site in the plan view of the integrated circuit.

9. The method of claim 1 , wherein the bonding and terminating steps are repeated for differential wire bond pairs having a first wire bond profile, then repeated for differential wire bond pairs having a second wire bond profile.

10. The method of claim 1 , wherein the proximate differential wire bond pairs have wire bond profiles with three segments.

11. The method of claim 1 wherein the proximate differential wire bond pairs have wire bond profiles with a continuous curve.

12. The method of claim 1 , wherein either the first bond sites or the second bond sites are bonded to a common die.

13. The method of claim 1 , wherein the bonding tool does not contact existing wire bonds in the bonding operation and wherein wire bonds are configured so that they are not in contact with one another.

14. An article of manufacture for performing a wire-bonding operation in an integrated circuit, utilizing a bonding tool, comprising a machine readable medium containing one or more programs which when executed implement the steps of:

bonding a wire to a first bond site in the integrated circuit; and

terminating the wire at a second bond site;

wherein the bonding and terminating steps are repeated for at least two differential wire bond pairs, wherein individual wires within each of the at least two differential wire bond pairs have substantially similar wire bond profiles, and wherein proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles; and

wherein individual wires within each of the at least two differential wire bond pairs are adjacent to each other without other wires therebetween in a plan view of the integrated circuit.

15. The article of manufacture of claim 14 , wherein the proximate differential wire bond pairs have wire bond profiles with different heights above the first bond site in the integrated circuit.

16. The article of manufacture of claim 14 , wherein the proximate differential wire bond pairs have wire bond profiles with different lengths from the first bond site in the integrated circuit.

17. The method of claim 1 , wherein the at least two differential wire bond pairs provide connections with a substrate for at least one of one or more circuit elements disposed on the substrate.

18. The article of manufacture of claim 14 , wherein the at least two differential wire bond pairs provide connections with a substrate for at least one of one or more circuit elements disposed on the substrate.

19. The article of manufacture of claim 14 , wherein the at least two differential wire bond pairs are staggered in length from the first bond site in the plan view of the integrated circuit.

20. The article of manufacture of claim 14 , wherein either the first bond sites or the second bond sites are bonded to a common die.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →