IP Library Granted Patent US 41,516
Granted Patent E1
US 41,516 · App. 11/324,119 · Granted Aug 17, 2010

Socketless/boardless test interposer card

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Quick Facts
Patent No.
US 41,516
App. No.
11/324,119
Granted
Aug 17, 2010
Kind
E1
Abstract

An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.

Claims (15)

1. An interposer card, comprising:

a top layer having the pads for mounting inputs and outputs (I/Os) of a test package; at least one middle layer having a plurality of traces and at least one bus bar for forming gangled ganged connections of all commonly biased test package I/Os; and a bottom layer having pads that replicate the test package inputs and output (I/Os) I/Os; and

pads for mounting I/Os of a test package;

edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and wherein the pads for replicating that replicate the test package I/Os for connecting connect the interposer card directly to an automated electrical testing (ATK) (ATE) system for performing ATE tests on the test package.

2. The interposer card of claim 1 wherein the ganged connections can be singulated by cutting the card along the bus bar.

3. The interposer card of claim 1 further including vias extending between the top layer, the middle layers, and the bottom layers for routing connections from the test package I/Os to each of the layers.

4. The interposer card of claim 3 wherein the edge card connectors supply external electrical connections to the interposer card during the B/H/T test.

5. The interposer card of claim 4 wherein the edge card connectors are located along at least two edges of the interposer card and arranged in quadrants.

6. The interposer card of claim 4 wherein the edge card connectors are located on top and bottom layers of the interposer card.

7. The interposer card of claim 3 wherein the at least one middle layer comprises an I/O Vss layer and and I/O Vdd layer.

8. The interposer card of claim 7 wherein the test package includes negative loop I/Os and positive loop I/Os, the I/O Vss layer including traces that connect all negative loop I/Os in parallel to a first bus bar, and the I/O Vdd layer including traces that connect all positive loop test package I/Os in parallel to a second bus bar.

9. The interposer card of claim 1 wherein the edge connectors connect to a universal stress board for HAST testing, such that sockets are unnecessary for mounting the interposer card.

10. The interposer card of claim 9 wherein the universal stress board includes multiple pairs of mating female connectors for receiving the edge card connectors of multiple interposer cards.

11. The interposer card of claim 10 wherein the each pair of mating female connectors includes a stationary clamp for receiving one side of the interposer card, and an adjustable clamp for receiving the other side of the interposer card.

12. The interposer card of claim 11 wherein the adjustable clamp can be slid horizontally along the board in order to accommodate different sizes of interposer cards.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →