IP Library Granted Patent US 7,737,564
Granted Patent B2
US 7,737,564 · App. 11/334,870 · Granted Jun 15, 2010

Power configuration method for structured ASICs

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,737,564
App. No.
11/334,870
Granted
Jun 15, 2010
Kind
B2
Abstract

A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.

Claims (23)

1. A universal bond pad system for electrically coupling a bond pad of a configurable integrated circuit to an input/output device comprising:

an input/output device with at least one pin and at least one slice, the at least one pin including at least one of: an input/output power supply pin, an input/output core power supply pin, an input/output ground supply pin, and an input/output core ground supply pin, and the at least one slice including an input/output signal slice;

a bond pad with at least two layers; and

an interconnect structure for electrically coupling at least one layer of the at least two layers to the input/output device,

wherein the bond pad is configurable as at least two selected from the group of bond pad configurations consisting of: a power pad by being electrically coupleable via the interconnect structure to the input/output power supply pin of the at least one pin of the input/output device, a core power pad by being electrically coupleable via the interconnect structure to the input/output core power supply pin of the at least one pin of the input/output device, an input/output signal pad by being electrically coupleable via the interconnect structure to the input/output signal slice of the at least one slice of the input/output device, a ground pad by being electrically coupleable via the interconnect structure to the input/output ground supply pin of the at least one pin of the input/output device, or a core ground pad by being electrically coupleable via the interconnect structure to the input/output core ground supply pin of the at least one pin of the input/output device,

wherein the bond pad configuration is determined by which pin of the at least one pin is electrically coupled to the bond pad and which slice of the at least one slice is electrically coupled to the input/output device.

2. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure transfers an input/output signal.

3. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure transfers an input/output power supply.

4. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure transfers an input/output ground supply.

5. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure transfers a core power supply.

6. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure transfers a core ground supply.

7. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure is a pad wire.

8. The universal bond pad system as claimed in claim 1 , wherein the interconnect structure is a flip chip bump.

9. A universal bond pad system, comprising:

a bond pad with at least two layers;

an input/output device with at least two pins and at least one slice, the at least two pins including at least two of: an input/output power supply pin, an input/output core power supply pin, an input/output ground supply pin, and an input/output core ground supply pin, and the at least one slice including an input/output signal slice;

a pad structure assembly for electrically coupling a layer of the at least two layers to the input/output device,

wherein the bond pad is configurable as at least three selected from the group of bond pad configurations consisting of: a power pad by being electrically coupled to the input/output power supply pin of the at least two pins of the input/output device via the pad structure, a core power pad by being electrically coupled to the input/output core power supply pin of the at least two pins of the input/output device via the pad structure, an input/output signal pad by being electrically coupled to the input/output signal slice of the at least one slice of the input/output device via the pad structure, a ground pad by being electrically coupled to the input/output ground supply pin of the at least two pins of the input/output device via the pad structure, or a core ground pad by being electrically coupled to the input/output core ground supply pin of the at least two pins of the input/output device via the pad structure,

wherein the bond pad configuration is determined by which pin of the at least two pins is electrically coupled to the bond pad and which slice of the at least one slice is electrically coupled to the input/output device,

wherein each pin of the at least two pins is a different horizontal distance from the bond pad.

10. The universal bond pad system as claimed in claim 9 , further comprising a pad wire for coupling said layer of the at least two layers to said input/output signal pin of the input/output device.

11. The universal bond pad system as claimed in claim 9 , wherein the pad structure assembly includes a pad structure for transferring one selected from an input/output power supply and an input/output ground supply.

12. The universal bond pad system as claimed in claim 9 , wherein the pad structure assembly includes a pad structure for transferring an input/output core power supply and a pad structure for transferring an input/output core ground supply.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Mar 1, 2010
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 024003/0566 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2006
From: ALI, ANWAR; LAU, TAUMAN T.; DODDAPANENI, KALYAN
To: LSI LOGIC CORPORATION
Reel/Frame 017493/0795 →