IP Library Granted Patent US 7,776,648
Granted Patent B2
US 7,776,648 · App. 12/160,233 · Granted Aug 17, 2010

High thermal performance packaging for circuit dies

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Quick Facts
Patent No.
US 7,776,648
App. No.
12/160,233
Granted
Aug 17, 2010
Kind
B2
Abstract

A circuit die is disposed into a region defined by a mold. A molding material is then introduced into the region to encapsulate the circuit die. Prior to substantial curing of the molding material, at least a portion of the molding material is removed from over a surface of the circuit die, creating a recessed region in the encapsulating material. A heat spreader may then be disposed within the recessed region, as well as over the top surface of the encapsulating material. The heat spreader may have a downset that substantially aligns with the recessed region and reduces the distance between the heat spreader and the spacer for better heat dissipation.

Claims (24)

1. A packaging method for a circuit die comprising:

encapsulating a circuit component with molding material, the circuit component comprising a circuit die, an inner surface of a top mold plate used for containing the molding material during encapsulation being spaced vertically from a top surface of the circuit component during the encapsulating step so that the molding material forms a continuous top surface that covers and fully encapsulates the circuit component and at least a portion of a top surface of a substrate on which the circuit component is disposed;

removing at least a portion of the molding material over the circuit die to create a recessed region within the molding material; and

disposing a heat spreader over the recessed region of the molding material, a bottom surface of the heat spreader having a first downset disposed within the recessed region while a remainder of the bottom surface of the heat spreader is aligned with a top surface of the molding material, a top surface of the heat spreader having a second downset disposed over and aligned with at least a portion of the recessed region.

2. The method of claim 1 further comprising disposing an adhesive layer over at least a portion of the surface around or within the recessed region prior to disposing the heat spreader over the molding material and recessed region.

3. The method of claim 1 wherein substantially all of the molding material over at least a portion of the circuit die is removed to create the recessed region, and to minimize a distance between the circuit die and the heat spreader.

4. The method of claim 1 further comprising performing a curing procedure to cure the molding material.

5. The method of claim 4 wherein the curing procedure is performed after creating the recessed region.

6. The method of claim 1 wherein a laser is used to remove the portion of the molding material.

7. The method of claim 1 wherein encapsulating the circuit die comprises:

disposing the circuit component within a cavity defined by a mold, the cavity forming a gap between the circuit component and the mold plate; and

introducing molding material into the cavity that fills the gap.

8. The method of claim 7 wherein a distance between an upper mold plate and a lower mold plate forming the mold is substantially greater than a height of the circuit component.

9. The method of claim 1 wherein an inner surface of a top mold plate used for containing the molding material during encapsulation is spaced vertically from a top surface of the circuit component during the encapsulating step so that the molding material forms a continuous top surface that covers and fully encapsulates the circuit component and at least a portion of a top surface of a substrate on which the circuit component is disposed.

10. An electronic device comprising:

a substrate;

external contacts electrically connected to the substrate;

a circuit die electrically connected to the substrate and having a first surface and a second surface, the second surface mechanically coupled to the substrate;

molding material encapsulating at least a portion of the substrate and at least a portion of the circuit die, the molding material forming a recessed region over the first surface; and

a heat spreader thermally coupled to the circuit die, a bottom surface of the heat spreader having a first downset disposed within the recessed region while a remainder of the bottom surface of the heat spreader is aligned with a top surface of the molding material, a top surface of the heat spreader having a second downset disposed over and aligned with at least a portion of the recessed region.

11. The electronic device of claim 10 further comprising a spacer disposed between the recessed region and the first surface of the circuit die.

12. The electronic device of claim 11 wherein a top surface of the spacer is not covered by molding material.

13. The electronic device of claim 10 wherein the first surface is not covered by the molding material.

14. The electronic device of claim 10 wherein the molding material forms a continuous top surface that covers and fully encapsulates the circuit die and at least a portion of a top surface of the substrate.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →