IP Library Granted Patent US 7,443,042
Granted Patent B2
US 7,443,042 · App. 11/385,245 · Granted Oct 28, 2008

Methods and apparatus for wire bonding with wire length adjustment in an integrated circuit

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Quick Facts
Patent No.
US 7,443,042
App. No.
11/385,245
Granted
Oct 28, 2008
Kind
B2
Abstract

An integrated circuit is wire bonded in a manner such that there is consistent RF performance from integrated circuit package to integrated circuit package. Bond distances within the integrated circuit are measured, each corresponding to a wire bond to be formed. An area under a hypothetical wire bond profile is calculated as a function of the bond distances, a baseline wire length, and a baseline loop height. A wire is bonded across a given one of the bond distances to form a given one of the wire bonds. A wire bond profile for the given wire bond is provided having an area thereunder that is substantially equal to the calculated area.

Claims (7)

1. An integrated circuit comprising:

an integrated circuit package;

a plurality of circuit elements disposed within the integrated circuit package; and

a plurality of wire bonds; whereby the plurality of wire bonds are formed by the steps of: (i) measuring a plurality of bond distances within the integrated circuit, each bond distance corresponding to one of the plurality of wire bonds to be formed; (ii) calculating an area under a hypothetical wire bond profile as a function of the plurality of bond distances, a baseline wire length, and a baseline loop height; and (iii) bonding a wire across a given one of the plurality of bond distances to form a given one of the plurality of wire bonds; the bonding step being configured to provide a wire bond profile for the given wire bond having an area thereunder that is substantially equal to the calculated area in step (ii).

2. The integrated circuit of claim 1 , wherein the integrated circuit comprises a radio frequency (RF) integrated circuit.

3. The integrated circuit of claim 1 , wherein the integrated circuit comprises a plurality of dies.

4. The integrated circuit of claim 3 , wherein the integrated circuit comprises a plurality of capacitors, one or more of the dies being disposed between a corresponding pair of the capacitors.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →