I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process
View Patent ↗A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.
1. An ESD protection circuit configured to introduce a substrate-biased effect, formed on a P-type semiconductor substrate, for I/O pin protection against both positive and negative ESD stress conditions, comprising:
a first P-type well formed on the P-type semiconductor substrate, not hard-wired to VSS but shorted to VSS through the P-type semiconductor substrate;
a second P-type well formed on the P-type semiconductor substrate hard-wired to VSS;
multi-finger nMOS transistors formed on the first P-type well comprising source regions, hard-wired to VSS, drain regions, hard-wired to an I/O pad, and gate regions, hard-wired to VSS;
a N-type well ring formed on the P-type semiconductor substrate, hard-wired to the I/O pad, and disposed between the first P-type well and the second P-type well, wherein the first P-type well is isolated from the second P-type well;
a pMOSFET formed on the P-type semiconductor substrate, comprising a source node, connected to the I/O pad, a drain node, connected to a P-type diffusion ring formed on the first P-type well, and a gate node, connected to VDD;
wherein the P-type diffusion ring is formed on the first P-type well, hard-wired to a drain node of the pMOSFET, not hard-wired to VSS, but shorted to VSS through the P-type semiconductor substrate.
2. The ESD protection circuit as recited in claim 1 , wherein the N-type well ring is hard-wired to the I/O pad and thus suppresses a substrate current flowing to VSS through the second P-type well such that a trigger voltage of the multi-finger nMOS transistors can be lowered in a positive ESD stress event.
3. The ESD protection circuit as recited in claim 2 , wherein the trigger voltage of the multi-finger nMOS transistors is lowered such that each of the multi-finger nMOS transistors becomes a non-snapback ESD protection device, wherein the trigger voltage is lower than a holding voltage.
4. The ESD protection circuit as recited in claim 1 , wherein the N-type well ring is hard-wired to the I/O pad such that a negative ESD current can flow from the second P-type well to the N-type well, to avoid a negative ESD current flowing from the first P-type well to the second P-type well through the P-type semiconductor substrate.
5. The ESD protection circuit as recited in claim 1 , wherein the pMOSFET is turned on in a positive ESD stress condition such that a current is injected from the I/O pad into the first P-type well through the P-type diffusion ring.
6. The ESD protection circuit as recited in claim 5 , wherein the P-type diffusion ring is formed on the first P-type well and acts as a trigger node of the multi-finger nMOS transistors, wherein the trigger voltage of the multi-finger nMOS transistors is lowered.
7. The ESD protection circuit as recited in claim 1 , wherein the P-type semiconductor substrate has a 2˜6 Ohm·cm of resistivity.
8. The ESD protection circuit as recited in claim 1 , wherein the multi-finger nMOS transistors are unsilicided.
9. The ESD protection circuit as recited in claim 1 , wherein the nMOS transistors have at least 300 um of total width.
10. The ESD protection circuit as recited in claim 1 , further comprising a resistor connected to VSS and gates of the nMOS transistors.
11. The ESD protection circuit as recited in claim 10 , wherein the resistor has a resistance between 15,000 Ohms and 20,000 Ohms.