Dual-gate metal-oxide-semiconductor device
View Patent ↗An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
1. A method of forming a metal-oxide-semiconductor device having improved high-frequency characteristics, the method comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region; and
forming at least a second gate on the insulating layer substantially over the channel region and between the first gate and the second source/drain region, the second gate having a length over the channel region which is substantially greater than a length of the first gate over the channel region, the first and second gates being electrically isolated from one another;
wherein the metal-oxide-semiconductor device is configured such that a conduction of the channel region is selectively controllable as a function of first and second signals applied to the first and second gates, respectively.
2. The method of claim 1 , further comprising the steps of:
forming a first portion of the insulating layer under the first gate having a first thickness; and
forming a second portion of the insulating under the second gate having a second thickness, the second thickness being different than the first thickness.
3. The method of claim 1 , wherein the channel region is formed having a doping concentration level that is highest proximate the first source/drain region and decreases as the channel region extends toward the second source/drain region.
4. The method of claim 3 , wherein the channel region is formed having a doping concentration level that varies from about 1e18 to about 1e15 atoms per cubic centimeter.
5. The method of claim 1 , wherein the first and second gates are formed in a substantially non-overlapping arrangement relative to one another.
6. The method of claim 1 , wherein the second gate is formed so as to overlap at least a portion of the first gate.
7. The method of claim 1 , further comprising the step of forming a shielding structure proximate the upper surface of the semiconductor layer and at least partially between the second gate and the second source/drain region, the shielding structure being electrically connected to the first source/drain region and electrically isolated from the first and second gates.
8. The method of claim 7 , wherein the shielding structure is formed so as to overlap at least a portion of the second gate.
9. The method of claim 1 , wherein the first and second gates are formed such that a ratio between the length of the second gate and the length of the first gate is greater than about 1.5.
10. A method of forming a metal-oxide-semiconductor device having improved high-frequency characteristics, the method comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region;
forming at least a second gate on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region, the second gate having a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another;
configuring the first gate for receiving a first signal in a first frequency range; and
configuring the second gate for receiving a second signal in a second frequency range, the first frequency range being higher than the second frequency range.
11. The method of claim 10 , wherein the second frequency range comprises substantially direct current components and the first frequency range comprises substantially radio frequency components.
12. A method of forming an integrated circuit having improved high-frequency performance, the method comprising the step of:
forming at least one metal-oxide-semiconductor device comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region; and
forming at least a second gate on the insulating layer substantially over the channel region and between the first gate and the second source/drain region, the second gate having a length over the channel region which is substantially greater than a length of the first gate over the channel region, the first and second gates being electrically isolated from one another;
wherein the metal-oxide-semiconductor device is configured such that a conduction of the channel region is selectively controllable as a function of first and second signals applied to the first and second gates, respectively.
13. The device of claim 12 , wherein the first and second gates are formed such that a ratio between the length of the second gate and the length of the first gate is greater than about 1.5.
14. The method of claim 12 , wherein forming the at least one metal-oxide-semiconductor device further comprises the step of forming a shielding structure proximate the upper surface of the semiconductor layer and at least partially between the second gate and the second source/drain region, the shielding structure being electrically connected to the first source/drain region and electrically isolated from the first and second gates.
15. A method of forming an integrated circuit having improved high-frequency performance, the method comprising the step of:
forming at least one metal-oxide-semiconductor device comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region; and
forming at least a second gate on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region, the second gate having a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another;
wherein the method of forming the integrated circuit further comprises configuring the at least one metal-oxide-semiconductor device such that a level of a first signal applied to the second gate is selectively controlled as a function of a level of a second signal applied to the first gate, so as to substantially maintain a linearity of the device over a desired range of levels of the first signal.
16. A method of forming an integrated circuit having improved high-frequency performance, the method comprising the steps of:
forming at least one metal-oxide-semiconductor device comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region; and
forming at least a second gate on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region, the second gate having a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another; and
forming a conditioning circuit in the integrated circuit, the conditioning circuit being formed having an input coupled to the first gate and an output coupled to the second gate, the conditioning circuit being configurable for generating a bias signal at the output for biasing the at least one metal-oxide-semiconductor device to a desired operating point, the bias signal being a function of an input signal applied to the input.
17. The method of claim 16 , further comprising configuring the conditioning circuit so as to be operative to increase a level of the bias signal for reducing at least one of an on-state resistance and a knee voltage of the device in response to an increased level of the input signal.
18. The method of claim 16 , further comprising configuring the conditioning circuit so as to be operative to shut off the at least metal-oxide-semiconductor device when the input signal exceeds a desired threshold level.
19. A method of forming an integrated circuit having improved high-frequency performance, the method comprising the step of:
forming at least one metal-oxide-semiconductor device comprising the steps of:
forming first and second source/drain regions of a first conductivity type in a semiconductor layer of a second conductivity type, the first and second source/drain regions being formed proximate an upper surface of the semiconductor layer and being spaced apart relative to one another;
forming a non-uniformly doped channel region of the second conductivity type in the semiconductor layer, proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions;
forming an insulating layer on at least a portion of the upper surface of the semiconductor layer;
forming a first gate on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region;
forming at least a second gate on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region, the second gate having a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another;
configuring the first gate for receiving a first signal in a first frequency range; and
configuring the second gate for receiving a second signal in a second frequency range, the first frequency range being higher than the second frequency range.