Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures
View Patent ↗A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.
1. An apparatus, comprising:
a substrate;
a deep n-well implanted in the substrate in an area of a capacitor structure;
a shallow trench isolation in the deep n-well, wherein the shallow trench isolation includes a crosshatch of insulator material;
a capacitor structure positioned over the shallow trench isolation; and
wherein the crosshatch of insulator material extends around the deep n-well, such that no deep n-well contact exists with remaining surface of the substrate.
2. The apparatus of claim 1 , wherein the substrate is a lightly p-doped semiconductor.
3. The apparatus of claim 2 , wherein the deep n-well is formed by implanting the lightly p-doped semiconductor with a dopant.
4. The apparatus of claim 3 , wherein the dopant is phosphorous.
5. The apparatus of claim 1 , wherein a depth of the deep n-well is within a range of 0.48 μm to 0.72 μm.
6. The apparatus of claim 1 , wherein a depth of the shallow french isolation is within a range of 0.32 μm and 0.48 μm.
7. The apparatus of claim 1 , wherein the shallow trench isolation forms substantially square sections of deep n-well at the surface of the substrate.
8. The apparatus of claim 7 , wherein each section of deep n-well at the surface of the substrate is approximately 1.2 μm wide.
9. The apparatus of claim 7 , wherein a width of each section of deep n-well at the surface of the substrate is approximately a length of a lowest metal layer of the capacitor structure divided by ten.
10. The apparatus of claim 1 , wherein the insulator material is silicon dioxide.