IP Library Granted Patent US 7,456,076
Granted Patent B2
US 7,456,076 · App. 11/506,659 · Granted Nov 25, 2008

Techniques for forming passive devices during semiconductor back-end processing

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Quick Facts
Patent No.
US 7,456,076
App. No.
11/506,659
Granted
Nov 25, 2008
Kind
B2
Abstract

Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Claims (27)

1. A method for forming a semiconductor device comprising:

forming a dielectric mask on a top surface of a semiconductor substrate, the semiconductor substrate containing a plurality of integrated devices;

etching recessed regions into a top surface of the dielectric mask;

filling the recessed regions with aluminum;

implanting the aluminum within each recessed region with a dopant material selected from among carbon and boron, to form a respective resistor; and

annealing the resistors to cause the dopant material to react with the aluminum to adjust the level of resistance in each resistor.

2. A method as recited in claim 1 further comprising:

etching recessed channels into the top surface of the dielectric mask wherein at least some of the recessed channels connect to respective recessed regions; and

filling in the recessed channels with aluminum to form conductive traces wherein some of the traces are integrally formed with the resistors that are formed in the recessed regions, wherein the conductive traces provide for electrical connectivity between integrated devices within the semiconductor substrate.

3. A method as recited in claim 1 further comprising operations that precede the operation of implanting the resistors, such operations including:

applying a photoresist layer over the dielectric mask and the resistors;

exposing the photoresist layer to a pattern of light;

developing the photoresist layer to expose the resistors; and

then proceeding onto the implanting process.

4. The method as recited in claim 3 wherein the photoresist layer is patterned so that the thickness of the photoresist layer is optimized to control the dosage of the dopant into recessed metal layers.

5. The method as recited in claim 3 wherein the photoresist layer is patterned so that the photoresist layer has at least a first thickness and a second thickness wherein the first thickness overlies a metal filled first recess and wherein the second thickness overlies a metal filled second recess and wherein the first thickness is different that the second thickness and whereby each the first and second thicknesses are optimized to control the dosage of the dopant into the associated underlying recessed metal layers and wherein said implanting results in resistors having different resistances.

6. A method as recited in claim 1 further comprising:

selecting a dosage of the dopant for implanting into the resistor in order to give the resistors a desired level of resistance.

7. A method as recited in claim 1 wherein the operation of filling the recessed channels and regions uses an electroplating processes.

8. A method as recited in claim 1 further comprising:

polishing the top surface of the dielectric mask and a top surface of the resistors such that the top surfaces of the dielectric mask and the resistors are substantially coplanar and flat.

9. The method as recited in claim 1 wherein the filling the recessed regions with aluminum comprises forming an aluminum layer on the dielectric mask to a thickness that is optimized to control the dosage of the dopant into the recessed aluminum.

10. A method for forming a semiconductor device comprising:

providing a semiconductor substrate having a plurality of integrated devices formed thereon;

defining a resistor sites for the substrate;

placing aluminum on the resistor sites; and

implanting the aluminum with a dopant material selected from among carbon and boron, to form resistors at the implanted aluminum sites.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →