Method of forming a low k polymer E-beam printable mechanical support
View Patent ↗A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.
1. A semiconductor integrated circuit comprising:
a low-k interconnect dielectric layer having an upper surface and a bottom surface; and
a plurality of support pillars formed by e-beam treatment, wherein the pillars are distributed in the low-k dielectric layer, wherein each of the plurality of pillars comprises a harder dielectric material than the bulk of the low-k dielectric layer, and wherein said support pillars each extend upward from the bottom surface of the dielectric layer to a point below the top surface of the dielectric layer such that a top surface of the pillars is covered by an upper portion of the dielectric layer.
2. The semiconductor integrated circuit as recited in claim 1 , wherein the plurality of pillars range from 0.02 to 0.5 μm in diameter.
3. The semiconductor integrated circuit as recited in claim 1 , wherein each of the plurality of pillars comprises a carbon silicon polymer.
4. The semiconductor integrated circuit as recited in claim 1 , wherein the harder dielectric material that forms the pillars comprises one of SiC, fluorinated silicate glass (FSG), and HSQ.
5. The semiconductor integrated circuit as recited in claim 1 , wherein the plurality of pillars are configured across the die in a predetermined pattern.
6. The semiconductor integrated circuit as recited in claim 5 , wherein the pattern is independent of the locations of the interconnect wires and vias in the low-k dielectric layer.
7. The semiconductor integrated circuit as recited in claim 1 , wherein each of the plurality of pillars is configured such that each pillar has a base portion and a top portion and wherein the base portion is wider than the top portion.
8. The semiconductor integrated circuit as recited in claim 1 , wherein the low-k dielectric layer includes conductive circuitry having conductive interconnects and wherein the plurality of pillars is arranged such that the pillars are formed in spaces between the interconnects.
9. The semiconductor integrated circuit as recited in claim 4 , wherein the plurality of pillars are doped with germanium.