Semiconductor device and process for reducing damaging breakdown in gate dielectrics
The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.
1. An integrated circuit, comprising:
a first type of transistors each having a gate structure with a first dopant concentration, the first type of transistors occupying a first area of a substrate surface and having a median time to hard breakdown; and
a second type of transistors each having a gate structure with a second dopant concentration higher than the first dopant concentration of the first type of transistors and occupying a second area of the substrate surface that is less than the first area, and having a shorter median time to hard breakdown than the first type of transistors, and wherein the first area comprises a substantial portion of a total area occupied by the first and second areas, the first and second types of transistors in the first and second areas being configured to have a same operating voltage and having a same channel structure.
2. The integrated circuit recited in claim 1 wherein the gate structures of the first type of transistors comprise a gate electrode and a resistor region.
3. The semiconductor device recited in claim 2 , wherein the gate electrode comprises a polysilicon having a given grain size and the resistor region comprises a polysilicon having a substantially larger grain size than the given grain size.
4. The semiconductor device recited in claim 3 , wherein the given grain size ranges from about 20 nm to about 50 nm and the substantially larger grain size ranges from about 80 nm to about 160 nm.
5. The integrated circuit recited in claim 2 , wherein the resistor region comprises polysilicon having a lower dopant concentration than the gate electrode.
6. The integrated circuit recited in claim 2 , wherein the gate electrode comprises a metal or metal silicide and the resistor region is a polysilicon having a dopant concentration.
7. The semiconductor device recited in claim 6 , wherein the dopant concentration of the polysilicon of the resistor region ranges from about 1E18 atoms/cm −3 to about 1E20 atoms/cm −3 .
8. The integrated circuit recited in claim 1 , wherein the first dopant concentration ranges from about 1E18 atoms/cm −3 to about 5E19 atoms/cm −3 and the second dopant concentration ranges from about 1E19 atoms/cm −3 to about 1E20 atoms/cm −3 .
9. The integrated circuit recited in claim 1 , wherein the first area comprises from about 80% to about 99.9% of a total area covered by the gate structures in the first and second areas.
10. The integrated circuit recited in claim 1 , wherein a resistivity of the gate structures of the first type of transistors is greater than a resistivity of the gate structures of the second type of transistors.