IP Library Granted Patent US 7,605,064
Granted Patent B2
US 7,605,064 · App. 11/438,493 · Granted Oct 20, 2009

Selective laser annealing of semiconductor material

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 7,605,064
App. No.
11/438,493
Granted
Oct 20, 2009
Kind
B2
Abstract

A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.

Claims (37)

1. A method for manufacturing an electronic product including a field effect transistor, comprising:

providing semiconductor material of a first conductivity type having a surface and two spaced-apart regions along the surface for receiving dopant of a second conductivity type;

forming a field effect transistor gate structure along the surface and over a third region of the surface between the two spaced apart regions;

providing dopant to the spaced-apart regions; and

spatially selectively heating the spaced apart regions to a temperature at least 50 degrees C. higher than a peak level of temperature which results in the third region when the spaced-apart regions are heated.

2. The method of claim 1 wherein upon heating the spaced-apart regions the dopant diffuses within the spaced-apart regions and electrically significant amounts of the dopant do not diffuse beyond the spaced-apart regions into other portions of the semiconductor material.

3. The method of claim 1 wherein the peak level of temperature of the gate structure resulting from heating the spaced-apart regions does not exceed 700 degrees C.

4. The method of claim 1 wherein the step of spatially selectively heating the spaced-apart regions is effected with a monochromatic laser tuned to 308 nm.

5. The method of claim 4 wherein the spaced-apart regions are heated to a temperature at least 300 degrees C. higher than the peak level of temperature which results in the third region when the spaced-apart regions are heated.

6. A method for manufacturing a semiconductor electronic product comprising:

providing semiconductor material having a surface region;

providing dopant to a portion of the surface region;

irradiating the portion of the surface region with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material, wherein the irradiating elevates the temperature of the portion of the surface region to render the dopant soluble in the semiconductor material.

7. The method of claim 6 wherein the step of irradiating renders the portion of the surface region liquid.

8. The method of claim 6 wherein the step of irradiating renders a portion of the semiconductor material including said portion of the surface region liquid and results in diffusion of the dopant about the liquid portion without electrically significant amounts of the dopant diffusing out of the liquid portion to other portions of the semiconductor material.

9. The method of claim 7 further comprising allowing the liquid to solidify.

10. A method for controlling movement of a dopant species in a semiconductor material comprising:

providing semiconductor material having a plurality of adjoining regions with a surface for formation of electronic devices;

introducing the dopant species along the surface of a first of the regions of the semiconductor material;

elevating the temperature of the first region of the semiconductor material relative to the temperature of a surrounding region of the semiconductor material such that the dopant diffuses within at least a portion of the first region.

11. The method of claim 10 wherein upon elevation of the temperature in the first region the temperature of the surrounding region remains lower than the minimum temperature required to effect thermal diffusion of the dopant species in the surrounding region.

12. The method of claim 10 wherein elevation of the temperature in the first region is of such limited time duration as to preclude diffusion of electrically significant amounts of the dopant species into the surrounding region.

13. A method for manufacturing a semiconductor electronic product comprising:

providing semiconductor material having a surface region with a layer of SiO 2 formed thereon and a layer of metal also formed thereon;

providing a dopant to a portion of the surface region;

irradiating the surface region by applying radiation of a wavelength such that the portion of the surface region containing the dopant absorbs sufficient radiation to diffuse the dopant into another portion of the semiconductor material and such that at least one of the layers formed on the surface region reflects said radiation.

14. The method of claim 13 wherein the layer of metal comprises tungsten silicide.

15. A method for manufacturing an electronic product including a field effect transistor, comprising:

providing semiconductor material of a first conductivity type having a surface and two spaced-apart regions along the surface for receiving dopant of a second conductivity type;

forming a field effect transistor gate structure along the surface and over a third region of the surface between the two spaced-apart regions;

providing dopant to the spaced-apart regions;

spatially selectively heating the spaced-apart regions but not the third region, with laser radiation.

16. A method for manufacturing an electronic product including a field effect transistor, comprising:

providing semiconductor material of a first conductivity type having a surface and two spaced-apart regions along the surface for receiving dopant of a second conductivity type;

forming a field effect transistor gate structure along the surface and over a third region of the surface between the two spaced-apart regions;

providing dopant to the spaced-apart regions;

spatially selectively heating the spaced-apart regions by applying radiation of a wavelength that is absorbed by the spaced-apart regions and reflected by a portion of the gate structure.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (2)
Division 0951600400 · Feb 29, 2000
Related Publication 20070001243A1 · Jan 4, 2007