IP Library Granted Patent US 8,119,501
Granted Patent B2
US 8,119,501 · App. 12/618,936 · Granted Feb 21, 2012

Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity

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Quick Facts
Patent No.
US 8,119,501
App. No.
12/618,936
Granted
Feb 21, 2012
Kind
B2
Abstract

Provided is a method for separating a semiconductor wafer into individual semiconductor dies. The method for separating the semiconductor wafer, among other steps, may include implanting an impurity into regions of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions. The method for separating the semiconductor wafer may further include separating the semiconductor wafer having the impurity into individual semiconductor dies along the weakened regions.

Claims (25)

1. A method for separating a semiconductor wafer into individual semiconductor dies, comprising:

placing an impurity into regions of a surface of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions;

removing a portion of an opposing surface of the semiconductor wafer after placing the impurity into the regions of the surface; and separating the semiconductor wafer having the impurity and the portion removed into individual semiconductor dies along the weakened regions;

wherein separating the semiconductor wafer includes separating the semiconductor wafer using mechanical or thermal stress.

2. The method of claim 1 wherein placing an impurity includes implanting rare gas ions into the regions.

3. The method of claim 1 wherein placing an impurity includes implanting hydrogen ions into the regions.

4. The method of claim 1 wherein the regions have a width of less than about 5 microns.

5. The method of claim 1 wherein the regions have a width of less than about 1 micron.

6. The method of claim 1 wherein the impurity is placed into the semiconductor wafer through openings in resist.

7. The method of claim 1 wherein the impurity is placed within scribe streets in the semiconductor wafer.

8. The method of claim 1 wherein separating the semiconductor wafer includes separating the semiconductor wafer using a roller to create the mechanical stress.

9. The method of claim 1 wherein the impurity is placed into a surface and further wherein the weakened regions extend substantially perpendicular to the surface.

10. A method for manufacturing semiconductor dies, comprising:

obtaining a semiconductor wafer; forming a plurality of semiconductor features on or in the semiconductor wafer; placing an impurity into regions of a surface of the semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions;

removing a portion of an opposing surface of the semiconductor wafer after placing the impurity into the regions of the surface; and

separating the semiconductor wafer having the semiconductor features impurity and portions removed into individual semiconductor dies along the weakened regions;

wherein separating the semiconductor wafer includes separating the semiconductor wafer using mechanical or thermal stress.

11. The method of claim 10 wherein placing an impurity includes implanting rare gas ions into the regions.

12. The method of claim 10 wherein placing an impurity includes implanting hydrogen ions into the regions.

13. The method of claim 10 wherein the regions have a width of less than about 5 microns.

14. The method of claim 10 wherein the regions have a width of less than about 1 micron.

15. The method of claim 10 wherein the impurity is placed into the semiconductor wafer through openings in resist.

16. The method of claim 10 wherein the impurity is placed within scribe streets in the semiconductor wafer.

17. The method of claim 10 wherein separating the semiconductor wafer includes separating the semiconductor wafer using a roller to create the mechanical stress.

18. The method of claim 10 wherein the impurity is placed into a surface and further wherein the weakened regions extend substantially perpendicular to the surface.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2009
From: HARRIS, EDWARD B.; STEINER, KURT G.
To: AGERE SYSTEMS INC.
Reel/Frame 023521/0301 →