Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank
An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
1. An IC capacitor bank, comprising:
a plurality of capacitor columns, wherein each of the capacitor columns includes:
a plurality of high dielectric constant (high-k) metal-insulator-metal (MIM) capacitors connected together in parallel by a pair of conductive traces, wherein one of the conductive traces is connected to a first supply line and the other is connected to a second supply line; and
a fusible trace located on an end of one of the pair of conductive traces that connects the parallel capacitors to one of the first or second supply lines, such that failure of a dielectric in one of the MIM capacitors in the parallel capacitors causes the fusible trace to at least partially open thereby limiting a fault current in one of the plurality of capacitor columns.
2. The IC capacitor bank as recited in claim 1 wherein the pair of supply lines provides two different ones selected from the group consisting of:
a current sourcing voltage;
a current sinking voltage; and
a common reference point.
3. The IC capacitor bank as recited in claim 1 wherein a width of the fusible trace is less than the narrower width of the pair of conductive traces connected to it such that a ratio of conductive trace width to fusible trace width ranges from about 9:1 to 12:1.
4. The IC capacitor bank as recited in claim 1 wherein the fusible trace provides a length to width ratio ranging from about 100:1 to 150:1.
5. The IC capacitor bank as recited in claim 1 wherein the fault current corresponds to a capacitor column current ranging from about one to five milliamperes.
6. The IC capacitor bank as recited in claim 1 wherein the fusible trace at least partially open corresponds to an electrical resistance increase of at least 50 times over an initial electrical resistance of the fusible trace.
7. The IC capacitor bank as recited in claim 1 wherein the fusible trace includes a fusing material that is selected from the group consisting of:
polycrystalline silicon;
silicided poly-silicon;
tantalum nitride; and
a fusible metal.
8. The IC capacitor bank as recited in claim 1 wherein the fusible trace includes a composite structure having a runner portion and a liner/barrier layer.
9. The IC capacitor bank as recited in claim 1 wherein the fusible trace includes a path liner that determines an increase in electrical resistance for limiting the fault current in the capacitor column.
10. The IC capacitor bank as recited in claim 9 wherein the path liner is a refractory metal liner.
11. A method of manufacturing an integrated circuit (IC) capacitor bank, comprising:
providing a plurality of capacitor columns wherein forming each of the capacitor columns further comprises:
providing a plurality of high dielectric constant (high-k) metal-insulator-metal (MIM) capacitors;
connecting the plurality of MIM capacitors together in parallel with a pair of conductive traces, wherein one of the conductive traces is connected to a first supply line and the other of the conductive traces is connected to a second supply line; and
locating a fusible trace on an end of one of the pair of conductive traces that connects the parallel capacitors to one of the first or second supply lines, such that failure of a dielectric in one of the MIM capacitors in the parallel capacitors causes the fusible trace to at least partially open thereby limiting a fault current in one of the plurality of capacitor columns.
12. The method as recited in claim 11 wherein locating the fusible trace includes the pair of supply lines providing two different ones selected from the group consisting of:
a current sourcing voltage;
a current sinking voltage; and
a common reference point.
13. The method as recited in claim 11 wherein locating the fusible trace includes providing a width of the fusible trace that is less than the narrower width of the pair of conductive traces connected to it such that a ratio of conductive trace width to fusible trace width ranges from about 9:1 to 12:1.
14. The method as recited in claim 11 wherein locating the fusible trace includes providing a length to width ratio of the fusible trace that ranges from about 100:1 to 150:1.
15. The method as recited in claim 11 wherein locating the fusible trace includes limiting the fault current in the capacitor column to a range of about one to five milliamperes.
16. The method as recited in claim 11 wherein locating the fusible trace includes providing for the fusible trace to at least partially open by increasing its electrical resistance by at least 50 times over its initial electrical resistance.
17. The method as recited in claim 11 wherein locating the fusible trace includes providing a fusing material that is selected from the group consisting of:
polycrystalline silicon;
silicided poly-silicon;
tantalum nitride; and
a fusible metal.
18. The method as recited in claim 11 wherein locating the fusible trace includes providing a composite structure for the fusible trace having a runner portion and a liner/barrier layer.
19. The method as recited in claim 11 wherein locating the fusible trace includes providing a path liner for the fusible trace that determines an increase in electrical resistance for limiting the fault current in the capacitor column.
20. The method as recited in claim 19 wherein locating the fusible trace includes providing the path liner as a refractory metal liner.